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[SYCL][ESIMD][EMU] Atomic update #6661
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[SYCL][ESIMD][EMU] Atomic update #6661
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dongkyunahn-intel
commented
Aug 29, 2022
- __esimd_svm_atomic0/1/2
- cmpxchng argument order fix (New value first, expected value second)
- atomic_add/sub/min/max/cmpxchg update
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'dword_atomic_smoke.cpp' from intel/llvm-test-suite fails with infinite looping. Still debugging. |
The test is disabled in intel/llvm-test-suite as the test fails for GPU as well - intel/llvm-test-suite#1185 |
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type __atomic_load_n (type *ptr, int memorder)
so AFAIU return __atomic_load_n((CmpxchgTy<Ty> *)ptr, __ATOMIC_SEQ_CST); does type conversion from CmpxchgTy<Ty> to Ty before returning the result, which is wrong. Do you have tests for this? They should have caught this problem.
| return __atomic_load_n((CmpxchgTy<Ty> *)ptr, __ATOMIC_SEQ_CST); | |
| return sycl::bit_cast<Ty>(__atomic_load_n((CmpxchgTy<Ty> *)ptr, __ATOMIC_SEQ_CST)); |
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I don't have a unit test for this. I'll put TODO comments with __ESIMD_UNSUPPORTED_ON_HOST.
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/verify with intel/llvm-test-suite#1259 |
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This is extremely dangerous, and can be a source of obscure bugs.
Emulator uses multiple threads to emulate GPU threads, so memory fence can't be a no-op.
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Fixed - built-in __atomic_thread_fence() is called.
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/verify with intel/llvm-test-suite#1274 |
1 similar comment
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/verify with intel/llvm-test-suite#1274 |
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Failures from ESIMD_EMULATOR are already handled in intel/llvm-test-suite#1274 |
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it looks strange that we need atomic_load as a part of atomic_store implementation, but that's how Gen ISA is :)
no action for this comment is needed
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Nit: strictly speaking, reinterpret_cast should be used. Can be fixed later.
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Here and in many more places:
Nit: sycl::bitcast should be used instead. Can be fixed later
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lsc_slm/surf/usm will be fixed once argument order for cmpxchg is confirmed. Other failures are handled in intel/llvm-test-suite#1274. |
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/verify with intel/llvm-test-suite#1274 |
1 similar comment
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/verify with intel/llvm-test-suite#1274 |
- __esimd_svm_atomic0/1/2 - cmpxchng argument order fix (New value first, expected value second) - atomic_add/sub/min/max/cmpxchg update
Co-authored-by: kbobrovs <Konstantin.S.Bobrovsky@intel.com>
- atomic intrinsic update and return value fix
- To be enabled later with unit test
- To prevent potential 'odr' failures from 'atomic_*' functions instantiated with same template argument
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Failures from 'SYCL / Linux / ESIMD Emu LLVM Test Suite (pull_request_target)' These tests are modified in intel/llvm-test-suite#1274 |
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/verify |