Add non-combinational CPU model #87

jardhu · 2019-09-20T00:15:15Z

This pull request implements a modified CPU model that accounts for memory stalling. In particular a new PipelinedNonCombinCPU class is added containing the design of this CPU, as well as a new hazard detection unit with signals for stalling the pipeline when the memory is busy.

Likewise new functionality was implemented for the testing drivers to allow the tester driver to specify what type of memory and ports are required for the test. This is used primarily to perform the instruction tests and full application tests for the non combinational CPU.

All existing test cases should default to using the combinational memory and combinational ports and retain the previous testing behavior, at least from what I tested.

Update master with new memory changes

This signal serves as a way for the pipeline to know whether the backing memory is ready for another request. This is required for the non-combinational memory to stall when the memory is not ready to continue. Previously, the 'good' signal served this purpose but is now used to write valid memory data to each stage's register.

jardhu · 2019-09-20T00:16:26Z

This should cover all of the new changes I had in the previous pull request with a cleaner commit history and none of the previous polluting commits. So, right now I just need to change the hazard detection unit and CPU to use the good/ready signals properly, and hopefully it should work.

src/main/scala/components/hazardmemstall.scala

powerjg · 2019-09-20T16:53:45Z

No worries :).

…

On Thu, Sep 19, 2019 at 5:19 PM Jared Barocsi ***@***.***> wrote: ***@***.**** commented on this pull request. ------------------------------ In src/main/scala/components/hazardmemstall.scala <#87 (comment)>: > + + // branch flush + when (io.exmem_taken) { + io.pcwrite := 1.U // use the PC from mem stage + io.ifid_flush := true.B + io.idex_bubble := true.B + io.exmem_bubble := true.B + } + + // mem stall + when (~(io.imem_good && io.dmem_good)) { + io.pcwrite := 2.U // freeze PC + io.idex_bubble := true.B + //io.exmem_bubble := true.B + } +} I noted the comment about my changes not having newlines at the end of files. My IDE is currently configured to add newlines right now and indeed my current copy of the repository has them. Maybe Git is stripping away the newline? I would have to check. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#87?email_source=notifications&email_token=AAA2YHCEJQR3JXB73KYMZFTQKQJH3A5CNFSM4IYRIRN2YY3PNVWWK3TUL52HS4DFWFIHK3DMKJSXC5LFON2FEZLWNFSXPKTDN5WW2ZLOORPWSZGOCFLNREA#pullrequestreview-290904208>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAA2YHDH6PPEK5IMLKLF5DLQKQJH3ANCNFSM4IYRIRNQ> .

-- Jason Lowe-Power (he/him/his) Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://arch.cs.ucdavis.edu/

jardhu · 2019-09-24T04:37:02Z

I'm having some trouble trying to get the non-combinational CPU to work with the signals; nothing I did before seems to work now. Could I perhaps talk with you about it on Wednesday?

jardhu · 2019-10-04T05:38:43Z

Issue with JAL:
The PC correctly jumps to the address specified by JAL, however the CPU does not properly "link" PC+4 to the registers. In the JAL tests, 8 is written instead of the correct value of 4.
Possible causes:
The CPU always starts with imem being busy, despite there being no incoming instruction or signal to do so.

Methodology to reproduce:

Clone or pull the changes up to 2201ebf.
Run testOnly dinocpu.PipelinedNonCombinCPUTester -- -z jal in sbt.
Some debugging statements should appear. Most notably, at the beginning,

IMEM READY: 0 DMEM READY: 1
Cycle 1: PC=>4 (8)
IMEM READY: 0 DMEM READY: 1
Cycle 2: PC=>4 (8)
IMEM READY: 0 DMEM READY: 1
Cycle 3: PC=>4 (8)
IMEM READY: 0 DMEM READY: 1
Cycle 4: PC=>4 (8)
IMEM READY: 1 DMEM READY: 1
---------------------------------------------
Cycle 5: PC=>4 (12)
IMEM READY: 0 DMEM READY: 1
Cycle 6: PC=>8 (12)
IMEM READY: 0 DMEM READY: 1
Cycle 7: PC=>8 (12)
IMEM READY: 0 DMEM READY: 1
Cycle 8: PC=>8 (12)
...```
On every cycle PC (after the arrow) and PC+4 (in the parenthesis) are displayed, as well as the states of memory below it. Lines are outputted whenever the CPU is not stalling to indicate a new memory request being pushed through.

This signal serves as a way for the pipeline to know whether the backing memory is ready for another request. This is required for the non-combinational memory to stall when the memory is not ready to continue. Previously, the 'good' signal served this purpose but is now used to write valid memory data to each stage's register.

This will probably be rebased so that it's merged in the commit that actually adds this class

jardhu · 2019-11-23T03:57:10Z

Nothing new here, I'm just updating my branch with all the changes to master :)

jardhu · 2019-11-23T04:02:21Z

One minor comment about the base branch changes: Apparently, it is by design that a feature branch with merged-in master commits shows these old commits in a pull request. Obviously we do not want these in the pull request's history, so a workaround to remove these is to change the base of the PR from master to a temporary branch and change it back.

… design

powerjg

Looking good! What's the current state? Does the new design pass the tests?

powerjg · 2020-01-02T21:57:41Z

src/main/scala/components/hazardmemstall.scala

+ * Output: exmem_disable, if true, explicitly prevent the EX/MEM register from being written to
+ *
+ * For more information, see Section 4.7 and beginning of 4.8 of Patterson and Hennessy
+ * This follows the "Data hazards and stalls" section and the "Assume branch not taken" section


Is this true or copied from somewhere else?

The new signals do not follow the pattern. Do you think I should move them beyond that note about the Patterson note and clarify that they are additionally added in?

I'd say just drop that part of the comment if it doesn't apply anymore. It's fine to go beyond the textbook :)

src/main/scala/components/hazardmemstall.scala

jardhu · 2020-01-03T02:03:50Z

R-type and I-type tests work. Branching and jumps still don't work, and memory does not work. By extension the small applications tests also fails.

I am working on the memory tests right now.

powerjg · 2020-01-03T16:38:27Z

BTW, Sorry if my recent commits cause any conflicts. However, if you rebase on master and update the file to work with the new single stepper printing system you should be able to debug more easily.

powerjg

A couple of small FYI's :)

powerjg · 2020-01-03T21:27:23Z

src/main/scala/testing/CPUTesterDriver.scala

@@ -15,7 +15,10 @@ class CPUFlatSpec extends FlatSpec with Matchers
 class CPUTesterDriver(cpuType: String,
                      branchPredictor: String,
                      binary: String,
-                      extraName: String = "") {
+                      extraName: String = "",
+                      forceDebug: Boolean = false,


force debug was removed in master, fyi.

powerjg · 2020-01-03T21:27:54Z

src/main/scala/testing/CPUTesterDriver.scala

    val cpustr = if (branchPredictor != "") { cpuType+"-bp" } else { cpuType }
-    val driver = new CPUTesterDriver(cpustr, branchPredictor, testCase.binary, testCase.extraName)
+    val driver = new CPUTesterDriver(cpustr, branchPredictor, testCase.binary, testCase.extraName, false,


Shouldn't need false here anymore.

powerjg · 2020-01-11T17:49:24Z

Getting closer :)

- Add dump function to the single stepper - Improve the instruction print function Still need to make the pipeline registers print nicely Closes jlpteaching#107 Closes jlpteaching#59 Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Closes jlpteaching#108 Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

powerjg · 2020-01-14T17:22:36Z

Looking good! It looks like it's pretty close!

Unfortunately this breaks branch instructions again.

jardhu · 2020-01-18T11:00:31Z

@powerjg All instruction unit tests pass, only the simple applications fail now. I won't be available for the next few days to look closer at what is happening, but could you perhaps give some insight onto specific architectural details each application is supposed to test? Or are they designed so that if every single unit test works, then the simple applications also should pass after?

powerjg · 2020-01-18T18:04:39Z

Well, the idea was that if you pass the instruction tests the full applications would work. However, in practice, it seems that there are some cases the instruction tests don't test well. We might be able to go back to Piazza from wq '19 and see what those cases were and develop some better tests :).

IIRC, the cases that weren't covered had to do with JAL and JALR, but I could be mis-remembering.

Jared Barocsi added 6 commits September 17, 2019 10:49

Merge pull request #3 from jlpteaching/master

6dd5567

Update master with new memory changes

Update .gitignore to ignore test files

6bddf9a

Create non-combin CPU model and a hazard w/ mem-stall module

0b1dc3b

Add tester functionality for new memory types

d752844

Correct memory test to observe new interface signals

a0bcf8b

jardhu commented Sep 20, 2019

View reviewed changes

src/main/scala/components/hazardmemstall.scala Show resolved Hide resolved

Jared Barocsi added 4 commits September 26, 2019 07:00

Fix R-type and I-type instructions

d26ffab

Fix memory instructions

756432f

Fix combin memory to observe ready/good signals

fcd1b77

Commit changes for review and identification of jump bug

2201ebf

Jared Barocsi added 11 commits November 22, 2019 19:43

Update .gitignore to ignore test files

704ef5c

Create non-combin CPU model and a hazard w/ mem-stall module

c93af9c

Add tester functionality for new memory types

a48682b

Correct memory test to observe new interface signals

97cbb31

Fix R-type and I-type instructions

0a3ce55

Fix memory instructions

8a3b3ad

Fix combin memory to observe ready/good signals

f6665ed

Commit changes for review and identification of jump bug

a610275

Move non-combin CPU into 'dinocpu.pipelined' package

b0d1b15

This will probably be rebased so that it's merged in the commit that actually adds this class

Fast forward master branch on non-combin-cpu branch

d058956

jardhu changed the base branch from master to update-memportio November 23, 2019 04:00

jardhu changed the base branch from update-memportio to master November 23, 2019 04:01

Jared Barocsi added 4 commits November 22, 2019 20:04

Fix an import statement in CPU configuration

1f2aa00

Merge master commits into non-combin-cpu

eccd4b8

Copy over regular pipelined CPU over non combinational, for new model…

f1a91a3

… design

Update mem stall hazard detector with new stall logic

f14b973

jardhu force-pushed the non-combin-cpu branch from b92342e to f14b973 Compare December 27, 2019 04:38

Jared Barocsi added 3 commits December 28, 2019 15:56

Fix non-combinational CPU module name

bbc8b4e

Fix hazard unit compilation errors and IO signal names

92c4beb

Fix R-type and I-type instructions in new non-combin CPU

bfa12e6

powerjg reviewed Jan 2, 2020

View reviewed changes

Fix non-multi-cycle memory instructions

b6cb493

powerjg reviewed Jan 3, 2020

View reviewed changes

Jared Barocsi and others added 6 commits January 14, 2020 08:08

Update jelf to 0.4.1

66219b2

Improve the single stepper

cdd3bb4

- Add dump function to the single stepper - Improve the instruction print function Still need to make the pipeline registers print nicely Closes jlpteaching#107 Closes jlpteaching#59 Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Remove debugging from Chisel in favor of singlestep

c739ce3

Closes jlpteaching#108 Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

Remove leftover debug prints in non-combin CPU

12f3b10

Fix sw memory instructions

e274f2b

Fix branch and jumps

2c44599

jardhu force-pushed the non-combin-cpu branch from 5d45339 to 2c44599 Compare January 14, 2020 16:12

Merge branch 'master' into non-combin-cpu

eabd6a2

Jared Barocsi added 3 commits January 14, 2020 18:34

Correct incorrect merge in CPUTesterDriver

4a989d6

Amend load hazard bubbling, fixing ld forwarding.

2e53b89

Unfortunately this breaks branch instructions again.

Fix branching and jump instructions

018fecd

jardhu force-pushed the non-combin-cpu branch from ae38a50 to 018fecd Compare January 18, 2020 10:50

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Add non-combinational CPU model #87

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Add non-combinational CPU model #87

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