Add non-combinational CPU model

.gitignore

@@ -349,3 +349,9 @@ simulator_run_dir
 # For containers
 *.sif
 .treadle_repl_history
+
+# For test binary files, since we need to force CWD to be the root of the dinocpu directory instead
+# of test_run_dir.
+*.hex
+*Top.datastore.snapshot.json
+*Top.lo.fir

src/main/scala/components/hazardmemstall.scala

@@ -0,0 +1,103 @@
+// This file contains the hazard detection unit
+
+package dinocpu
+
+import chisel3._
+
+/**
+ * The hazard detection unit, modified for memory stalling
+ *
+ * Input:  rs1, the first source register number
+ * Input:  rs2, the first source register number
+ * Input:  idex_memread, true if the instruction in the ID/EX register is going to read from memory
+ * Input:  idex_rd, the register number of the destination register for the instruction in the ID/EX register
+ * Input:  exmem_rd, the register number of the destination register for the instruction in the EX/MEM register
+ * Input:  exmem_taken, if true, then we are using the nextpc in the EX/MEM register, *not* pc+4.
+ * Input:  imem_good, high if instruction memory is idle and ready.
+ * Input:  dmem_good, high if data memory is idle and ready.
+ *
+ * Output: pcwrite, the value to write to the pc. If 0, pc+4, if 1 the next_pc from the memory stage,
+ *         if 2, then the last pc value (2 stalls the pipeline)
+ * Output: imem_disable, if true, prevent instruction memory from receiving requests
+ * Output: ifid_bubble, if true, we should insert a bubble in the IF/ID stage
+ * Output: ifid_disable, if true, explicitly prevent the IF/ID register from being written to
+ * Output: ifid_flush, if true, set the IF/ID register to 0
+ * Output: idex_bubble, if true, we should insert a bubble in the ID/EX stage
+ * Output: idex_disable, if true, explicitly prevent the ID/EX register from being written to
+ * Output: exmem_bubble, if true, we should insert a bubble in the EX/MEM stage
+ * Output: exmem_disable, if true, explicitly prevent the EX/MEM register from being written to
+ *
+ * For more information, see Section 4.7 and beginning of 4.8 of Patterson and Hennessy
+ * This follows the "Data hazards and stalls" section and the "Assume branch not taken" section
+ */
+class HazardUnitMemStall extends Module {
+  val io = IO(new Bundle {
+    val rs1           = Input(UInt(5.W))
+    val rs2           = Input(UInt(5.W))
+    val idex_memread  = Input(Bool())
+    val idex_rd       = Input(UInt(5.W))
+    val exmem_memread = Input(Bool())
+    val exmem_rd      = Input(UInt(5.W))
+    val exmem_taken   = Input(Bool())
+    val imem_ready    = Input(Bool())
+    val dmem_ready    = Input(Bool())
+    val dmem_good     = Input(Bool())
+
+    val pcwrite       = Output(UInt(2.W))
+    val ifid_bubble   = Output(Bool())
+    val ifid_disable  = Output(Bool())
+    val ifid_flush    = Output(Bool())
+    val idex_bubble   = Output(Bool())
+    val idex_disable  = Output(Bool())
+    val exmem_bubble  = Output(Bool())
+    val exmem_disable = Output(Bool())
+  })
+
+  // default
+  io.pcwrite       := 0.U
+  io.ifid_bubble   := false.B
+  io.ifid_disable  := false.B
+  io.ifid_flush    := false.B
+  io.idex_bubble   := false.B
+  io.idex_disable  := false.B
+  io.exmem_bubble  := false.B
+  io.exmem_disable := false.B
+
+  // Load to use hazard:
+  // Bubble ifid and idex when a load is in ex, or if it is in ex and the data memory
+  // hasn't responded with valid data yet (the read data must be present on dmem.io.readdata before we proceed)
+  when ((io.idex_memread && (io.idex_rd === io.rs1 || io.idex_rd === io.rs2)) ||
+        (io.exmem_memread || ! io.dmem_ready && (io.exmem_rd === io.rs1 || io.exmem_rd === io.rs2))) {
+    io.pcwrite     := 2.U
+    io.ifid_bubble := true.B
+    io.idex_bubble := true.B
+  }
+
+  // imem stall:
+  // Freeze the PC to preserve the current PC for the entire stall period,
+  // so that on un-stall the next PC points to the next instruction
+  // Disable exmem so that re-execution of the same instruction doesn't have any
+  // residual effect (jal)
+  when (! io.imem_ready) {
+    io.pcwrite       := 2.U
+    io.exmem_bubble := true.B
+  }
+
+  // dmem stall
+  // Freeze the PC to preserve the current PC for imem
+  // Disable writes for ID/EX
+  // Disable writes for EX/MEM
+  when (! io.dmem_ready) {
+    io.pcwrite := 2.U
+    io.idex_bubble  := true.B
+    io.exmem_bubble := true.B
+  }
+
+  // branch flush
+  when (io.exmem_taken) {
+    io.pcwrite := 1.U // use the PC from mem stage
+    io.ifid_flush   := true.B
+    io.idex_bubble  := true.B
+    io.exmem_bubble := true.B
+  }
+}

src/main/scala/configuration.scala

@@ -6,8 +6,7 @@ package dinocpu
 import java.io.File
 import dinocpu.components._
 import dinocpu.memory._
-import dinocpu.pipelined.PipelinedCPU
-import dinocpu.pipelined.PipelinedCPUBP
+import dinocpu.pipelined._
 
 /**
  * This class configures all of the dinocpus. It takes parameters for the type of CPU model
@@ -45,6 +44,7 @@ class CPUConfig
       case "single-cycle" => new SingleCycleCPU
       case "pipelined" => new PipelinedCPU
       case "pipelined-bp" => new PipelinedCPUBP
+      case "pipelined-non-combin" => new PipelinedNonCombinCPU
       case _ => throw new IllegalArgumentException("Must specify known CPU model")
     }
   }

src/main/scala/memory/base-memory-components.scala

@@ -55,6 +55,8 @@ abstract class BaseIMemPort extends Module {
   // ports internally assigning values to the, means that these DontCares
   // should be completely 'overwritten' when the CPU is elaborated
   io.bus      <> DontCare
+
+  io.pipeline.good := io.bus.response.valid
 }
 
 /**

src/main/scala/memory/memory-combin-ports.scala

@@ -12,6 +12,9 @@ import dinocpu.memory.MemoryOperation._
   * The I/O for this module is defined in [[IMemPortIO]].
   */
 class ICombinMemPort extends BaseIMemPort {
+  // Combinational memory is always ready
+  io.pipeline.ready := true.B
+
   // When the pipeline is supplying a high valid signal
   when (io.pipeline.valid) {
     val request = Wire(new Request)
@@ -26,7 +29,6 @@ class ICombinMemPort extends BaseIMemPort {
   }
 
   // When the memory is outputting a valid instruction
-  io.pipeline.good := true.B
   io.pipeline.instruction := io.bus.response.bits.data
 }
 
@@ -36,7 +38,8 @@ class ICombinMemPort extends BaseIMemPort {
   * The I/O for this module is defined in [[DMemPortIO]].
   */
 class DCombinMemPort extends BaseDMemPort {
-  io.pipeline.good := true.B
+  // Combinational memory is always ready
+  io.pipeline.ready := true.B
 
   when (io.pipeline.valid && (io.pipeline.memread || io.pipeline.memwrite)) {
     // Check that we are not issuing a read and write at the same time

src/main/scala/memory/memory-noncombin-ports.scala

@@ -17,12 +17,26 @@ class OutstandingReq extends Bundle {
 
 /**
  * The instruction memory port. Since both the combinational and noncombinational instruction ports just issue
- * read requests in the same way both ports have the same implementation
+ * read requests in the same way both ports share the same implementation
  *
  * The I/O for this module is defined in [[IMemPortIO]].
  */
 class INonCombinMemPort extends ICombinMemPort {
-  io.pipeline.good := io.bus.response.valid
+  // Non-combinational memory can technically always accept requests since they are delayed through a pipe.
+  // But we want to be able to signal that the memory is holding a request, so a register is used to store
+  // whether a request passed through this memory port
+  val imemBusy  = RegInit (false.B)
+
+  when (io.pipeline.valid) {
+    imemBusy := true.B
+  } .elsewhen (io.bus.response.valid) {
+    imemBusy := false.B
+  }
+
+  // Memory is ready when the backing memory responds with valid data, or the busy register is false.
+  // If io.bus.response.valid is true, then imemBusy must be false as the when statements above updates
+  // imemBusy on the next cycle.
+  io.pipeline.ready := (! imemBusy || io.bus.response.valid)
 }
 
 /**
@@ -31,6 +45,11 @@ class INonCombinMemPort extends ICombinMemPort {
  * The I/O for this module is defined in [[DMemPortIO]].
  */
 class DNonCombinMemPort extends BaseDMemPort {
+  // Non-combinational memory can technically always accept requests since they are delayed through a pipe.
+  // But we want to be able to signal that the memory is holding a request, so a register is used to store
+  // whether a request passed through this memory port
+  // In this case outstandingReq is adequate for this purpose, as outstandingReq.valid is true when this port is
+  // withholding either a read or write request
 
   // A register to hold intermediate data (e.g., write data, mask mode) while the request
   // is outstanding to memory.
@@ -46,7 +65,12 @@ class DNonCombinMemPort extends BaseDMemPort {
   // Ready if either we don't have an outstanding request or the outstanding request is a read and
   // it has been satisfied this cycle. Note: we cannot send a read until one cycle after the write has
   // been sent.
-  val ready = !outstandingReq.valid || (io.bus.response.valid && (outstandingReq.valid && outstandingReq.bits.operation === MemoryOperation.Read))
+  val wasRequestARead = outstandingReq.valid && outstandingReq.bits.operation === MemoryOperation.Read
+
+  val ready = !outstandingReq.valid || (io.bus.response.valid && wasRequestARead)
+
+  io.pipeline.ready := ready
+
   when (io.pipeline.valid && (io.pipeline.memread || io.pipeline.memwrite) && ready) {
     // Check if we aren't issuing both a read and write at the same time
     assert (! (io.pipeline.memread && io.pipeline.memwrite))

src/main/scala/memory/memory-port-io.scala

@@ -12,14 +12,17 @@ import chisel3._
  *
  * Input:  address, the address of a piece of data in memory.
  * Input:  valid, true when the address specified is valid
- * Output: good, true when memory is responding with a piece of data (used to un-stall the pipeline)
+ * Output: good, true when memory is responding with a piece of data (used to correctly write correct data to
+  *        each stage's register)
+ * Output: ready, true when the memory is ready to accept another request (used to un-stall the pipeline)
  *
  */
 class MemPortIO extends Bundle {
   // Pipeline <=> Port
   val address  = Input(UInt(32.W))
   val valid    = Input(Bool())
   val good     = Output(Bool())
+  val ready    = Output(Bool())
 }
 
 /**
@@ -30,6 +33,7 @@ class MemPortIO extends Bundle {
  *   Input:  valid, true when the address specified is valid
  *   Output: instruction, the requested instruction
  *   Output: good, true when memory is responding with a piece of data
+ *   Output: ready, true when the memory is ready to accept another request
  */
 class IMemPortIO extends MemPortIO {
   val instruction = Output(UInt(32.W))
@@ -48,6 +52,7 @@ class IMemPortIO extends MemPortIO {
  *   Input:  sext, true if we should sign extend the result
  *   Output: readdata, the data read and sign extended
  *   Output: good, true when memory is responding with a piece of data
+ *   Output: ready, true when the memory is ready to accept another request
  */
 class DMemPortIO extends MemPortIO {
   // Pipeline <=> Port