-
Notifications
You must be signed in to change notification settings - Fork 146
Add support arena atomics for RV64 #9329
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
base: bpf-next_base
Are you sure you want to change the base?
Conversation
Upstream branch: 42be23e |
Upstream branch: 42be23e |
545d750
to
6a566e4
Compare
ffefc6d
to
4ccf98a
Compare
Upstream branch: 42be23e |
6a566e4
to
b6f1602
Compare
4ccf98a
to
95edab2
Compare
There's a lot of redundant code related to store from register operations, let's extract emit_stx() to make code more compact. Signed-off-by: Pu Lehui <pulehui@huawei.com>
There's a lot of redundant code related to store from immediate operations, let's extract emit_st() to make code more compact. Signed-off-by: Pu Lehui <pulehui@huawei.com>
There's a lot of redundant code related to load into register operations, let's extract emit_ldx() to make code more compact. Signed-off-by: Pu Lehui <pulehui@huawei.com>
RV64 bpf is going to support ZACAS instructions. Let's separate toolchain support dependency from RISCV_ISA_ZACAS. Signed-off-by: Pu Lehui <pulehui@huawei.com>
Add rv_ext_enabled macro to check whether the runtime detection extension is enabled. Signed-off-by: Pu Lehui <pulehui@huawei.com>
Add Zacas instructions introduced by [0] to reduce code size and improve performance of RV64 JIT. Link: https://github.com/riscvarchive/riscv-zacas/releases/download/v1.0/riscv-zacas.pdf [0] Signed-off-by: Pu Lehui <pulehui@huawei.com>
Optimize cmpxchg instruction with amocas.w and amocas.d Zacas instructions. Signed-off-by: Pu Lehui <pulehui@huawei.com>
Upstream branch: 95993dc |
Add ex_insn_off and ex_jmp_off fields to struct rv_jit_context so that add_exception_handler() does not need to be immediately followed by the instruction to add the exception table. ex_insn_off indicates the offset of the instruction to add the exception table, and ex_jmp_off indicates the offset to jump over the faulting instruction. This is to prepare for adding the exception table to atomic instructions later, because some atomic instructions need to perform zext or other operations. Signed-off-by: Pu Lehui <pulehui@huawei.com>
Add arena atomics support for RMW atomics and load-acquire and store-release instructions. Non-Zacas cmpxchg is implemented via loop, which is not currently supported because it requires more complex extable and loop logic. Signed-off-by: Pu Lehui <pulehui@huawei.com>
Enable arena atomics tests for RV64. Signed-off-by: Pu Lehui <pulehui@huawei.com>
b6f1602
to
bc2eece
Compare
Pull request for series with
subject: Add support arena atomics for RV64
version: 1
url: https://patchwork.kernel.org/project/netdevbpf/list/?series=983958