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mtvec vectored mode #3092

mtvec vectored mode

mtvec vectored mode #3092

Triggered via pull request November 25, 2024 22:16
Status Success
Total duration 16m 47s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
36s
Synthesize full core
Build regression tests (riscv-tests)
39s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
43s
Build regression tests (riscv-arch-test)
Run unit tests
6m 56s
Run unit tests
Check code formatting and typing
27s
Check code formatting and typing
Run regression tests (riscv-tests)
6m 8s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
15m 42s
Run regression tests (riscv-arch-test)
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Artifacts

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Name Size
verilog-full-core
545 KB