mtvec vectored mode #3092
main.yml
on: pull_request
Synthesize full core
36s
Build regression tests (riscv-tests)
39s
Build regression tests (riscv-arch-test)
43s
Run unit tests
6m 56s
Check code formatting and typing
27s
Run regression tests (riscv-tests)
6m 8s
Run regression tests (riscv-arch-test)
15m 42s
Artifacts
Produced during runtime
Name | Size | |
---|---|---|
verilog-full-core
|
545 KB |
|