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Synchronous register file using MemoryBank #3112

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Synchronous register file using MemoryBank

Synchronous register file using MemoryBank #3112

Triggered via pull request November 29, 2024 11:26
@tilktilk
synchronize #765
tilk:rf-memorybank
Status Success
Total duration 15m 14s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
33s
Synthesize full core
Build regression tests (riscv-tests)
41s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
44s
Build regression tests (riscv-arch-test)
Run unit tests
7m 13s
Run unit tests
Check code formatting and typing
37s
Check code formatting and typing
Run regression tests (riscv-tests)
4m 40s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
14m 10s
Run regression tests (riscv-arch-test)
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Artifacts

Produced during runtime
Name Size
verilog-full-core
547 KB