Refactor RISC-V instruction models #2547
xThaidmain.yml
on: pull_request
Synthesize full core
41s
Build regression tests (riscv-tests)
58s
Build regression tests (riscv-arch-test)
51s
Run unit tests
6m 44s
Check code formatting and typing
1m 4s
Run regression tests (riscv-tests)
4m 16s
Run regression tests (riscv-arch-test)
12m 43s
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
verilog-full-core
Expired
|
323 KB |
|