Remove dead code

kuznia-rdzeni · Nov 26, 2024 · 26d074e · 26d074e
1 parent 8a4f0bf
commit 26d074e
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Showing 2 changed files with 2 additions and 4 deletions.
diff --git a/coreblocks/core_structs/rf.py b/coreblocks/core_structs/rf.py
@@ -5,7 +5,6 @@
 from coreblocks.params import GenParams
 from transactron.lib.metrics import HwExpHistogram, TaggedLatencyMeasurer
 from transactron.utils.amaranth_ext.functions import popcount
-from transactron.utils.transactron_helpers import make_layout
 
 __all__ = ["RegisterFile"]
 
@@ -14,7 +13,6 @@ class RegisterFile(Elaboratable):
     def __init__(self, *, gen_params: GenParams):
         self.gen_params = gen_params
         layouts = gen_params.get(RFLayouts)
-        self.internal_layout = make_layout(("reg_val", gen_params.isa.xlen), ("valid", 1))
         self.read_layout = layouts.rf_read_out
         self.entries = memory.Memory(shape=gen_params.isa.xlen, depth=2**gen_params.phys_regs_bits, init=[])
         self.valids = Array(Signal(init=k == 0) for k in range(2**gen_params.phys_regs_bits))

diff --git a/coreblocks/scheduler/scheduler.py b/coreblocks/scheduler/scheduler.py
@@ -304,8 +304,8 @@ def elaborate(self, platform):
             data = {
                 # when operand value is valid the convention is to set operand source to 0
                 "rs_data": {
-                    "rp_s1": Mux(source1.valid | flushing, 0, instr.regs_p.rp_s1),
-                    "rp_s2": Mux(source2.valid | flushing, 0, instr.regs_p.rp_s2),
+                    "rp_s1": Mux(source1.valid, 0, instr.regs_p.rp_s1),
+                    "rp_s2": Mux(source2.valid, 0, instr.regs_p.rp_s2),
                     "rp_s1_reg": instr.regs_p.rp_s1,
                     "rp_s2_reg": instr.regs_p.rp_s2,
                     "rp_dst": instr.regs_p.rp_dst,