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[FMV][AArch64] Remove features which expose non exploitable runtime b…
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…ehavior. (llvm#114387)

Features ebf16, memtag3, and rpres allow existing instructions to behave
differently depending on the value of certain control registers. FMV
does not read the content of control registers making these features
unsuitable for runtime dispatch. See the ACLE patch for more info:
ARM-software/acle#355
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@labrinea
labrinea authored Nov 7, 2024
1 parent f8b9616 commit e8b7d8b
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Showing 11 changed files with 29 additions and 47 deletions.
4 changes: 2 additions & 2 deletions clang/test/CodeGen/aarch64-cpu-supports-target.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,15 +9,15 @@ int check_all_feature() {
return 3;
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
return 4;
else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve"))
else if (__builtin_cpu_supports("i8mm+bf16+sve"))
return 5;
else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm"))
return 6;
else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128"))
return 7;
else if (__builtin_cpu_supports("sve2-bitperm+sve2-sha3+sve2-sm4"))
return 8;
else if (__builtin_cpu_supports("sme+memtag+memtag3+sb"))
else if (__builtin_cpu_supports("sme+memtag+sb"))
return 9;
else if (__builtin_cpu_supports("predres+ssbs+ssbs2+bti+ls64+ls64_v"))
return 10;
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13 changes: 2 additions & 11 deletions clang/test/CodeGen/aarch64-fmv-dependencies.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
// CHECK: define dso_local i32 @fmv._Maes() #[[aes:[0-9]+]] {
__attribute__((target_version("aes"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] {
// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16:[0-9]+]] {
__attribute__((target_version("bf16"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mbti() #[[bti:[0-9]+]] {
Expand All @@ -30,9 +30,6 @@ __attribute__((target_version("dpb"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mdpb2() #[[dpb2:[0-9]+]] {
__attribute__((target_version("dpb2"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mebf16() #[[bf16_ebf16:[0-9]+]] {
__attribute__((target_version("ebf16"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mf32mm() #[[f32mm:[0-9]+]] {
__attribute__((target_version("f32mm"))) int fmv(void) { return 0; }

Expand Down Expand Up @@ -75,9 +72,6 @@ __attribute__((target_version("lse"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mmemtag() #[[memtag:[0-9]+]] {
__attribute__((target_version("memtag"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag:[0-9]+]] {
__attribute__((target_version("memtag3"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] {
__attribute__((target_version("mops"))) int fmv(void) { return 0; }

Expand All @@ -99,9 +93,6 @@ __attribute__((target_version("rdm"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mrng() #[[rng:[0-9]+]] {
__attribute__((target_version("rng"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Mrpres() #[[ATTR0:[0-9]+]] {
__attribute__((target_version("rpres"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
__attribute__((target_version("sb"))) int fmv(void) { return 0; }

Expand Down Expand Up @@ -163,7 +154,7 @@ int caller() {
}

// CHECK: attributes #[[aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[bf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
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20 changes: 10 additions & 10 deletions clang/test/CodeGen/attr-target-version.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,15 +27,15 @@ int foo() {
inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; }
inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; }
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void) { return 11; }
inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; }
inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
Expand Down Expand Up @@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 8
Expand Down Expand Up @@ -736,7 +736,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3
// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 11
Expand Down Expand Up @@ -789,12 +789,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864726312827224064
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864726312827224064
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864708720641179648
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720641179648
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3MmopsMrcpc3
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
// CHECK: resolver_else2:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 893353197568
Expand Down Expand Up @@ -845,12 +845,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve
// CHECK: resolver_else14:
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 134348800
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134348800
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
// CHECK: resolver_return15:
// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16
// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Mdit
// CHECK: resolver_else16:
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
Expand Down
10 changes: 5 additions & 5 deletions clang/test/CodeGenCXX/attr-target-version.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

int __attribute__((target_version("sme-f64f64+bf16"))) foo(int) { return 1; }
int __attribute__((target_version("default"))) foo(int) { return 2; }
int __attribute__((target_version("sm4+ebf16"))) foo(void) { return 3; }
int __attribute__((target_version("sm4+bf16"))) foo(void) { return 3; }
int __attribute__((target_version("default"))) foo(void) { return 4; }

struct MyClass {
Expand Down Expand Up @@ -84,7 +84,7 @@ int bar() {
// CHECK-NEXT: ret i32 2
//
//
// CHECK-LABEL: define dso_local noundef i32 @_Z3foov._Mebf16Msm4(
// CHECK-LABEL: define dso_local noundef i32 @_Z3foov._Mbf16Msm4(
// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: ret i32 3
Expand Down Expand Up @@ -249,12 +249,12 @@ int bar() {
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435488
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435488
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217760
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217760
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
// CHECK: [[RESOLVER_RETURN]]:
// CHECK-NEXT: ret ptr @_Z3foov._Mebf16Msm4
// CHECK-NEXT: ret ptr @_Z3foov._Mbf16Msm4
// CHECK: [[RESOLVER_ELSE]]:
// CHECK-NEXT: ret ptr @_Z3foov.default
//
Expand Down
2 changes: 1 addition & 1 deletion clang/test/Sema/aarch64-cpu-supports.c
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ int test_aarch64_features(void) {
if (__builtin_cpu_supports("pmull128"))
return 3;
// expected-warning@+1 {{invalid cpu feature string}}
if (__builtin_cpu_supports("sve2,rpres"))
if (__builtin_cpu_supports("sve2,sve"))
return 4;
// expected-warning@+1 {{invalid cpu feature string}}
if (__builtin_cpu_supports("dgh+sve2-pmull"))
Expand Down
4 changes: 2 additions & 2 deletions clang/test/Sema/attr-target-clones-aarch64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
// expected-note@-2 {{previous declaration is here}}
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
int __attribute__((target_clones("dgh+rpres", "ebf16+dpb", "default"))) redecl4(void) { return 1; }
int __attribute__((target_clones("dgh", "bf16+dpb", "default"))) redecl4(void) { return 1; }

int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
Expand Down Expand Up @@ -69,7 +69,7 @@ empty_target_5(void);
void __attribute__((target_clones("sve2-bitperm", "sve2-bitperm")))
dupe_normal(void);

void __attribute__((target_clones("default"), target_clones("memtag3+bti"))) dupe_normal2(void);
void __attribute__((target_clones("default"), target_clones("memtag+bti"))) dupe_normal2(void);

int mv_after_use(void);
int useage(void) {
Expand Down
2 changes: 1 addition & 1 deletion clang/test/SemaCXX/attr-target-version.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ int __attribute__((target_version("flagm2"))) diff_link2(void) { return 1; }
extern int __attribute__((target_version("flagm"))) diff_link2(void);

namespace {
static int __attribute__((target_version("memtag3"))) diff_link2(void) { return 2; }
static int __attribute__((target_version("memtag"))) diff_link2(void) { return 2; }
int __attribute__((target_version("sve2-bitperm"))) diff_link2(void) { return 1; }
} // namespace

Expand Down
6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,8 @@ enum CPUFeatures {
FEAT_DGH,
FEAT_I8MM,
FEAT_BF16,
FEAT_EBF16,
FEAT_RPRES,
RESERVED_FEAT_EBF16, // previously used and now ABI legacy
RESERVED_FEAT_RPRES, // previously used and now ABI legacy
FEAT_SVE,
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
Expand All @@ -67,7 +67,7 @@ enum CPUFeatures {
FEAT_SME,
RESERVED_FEAT_MEMTAG, // previously used and now ABI legacy
FEAT_MEMTAG2,
FEAT_MEMTAG3,
RESERVED_FEAT_MEMTAG3, // previously used and now ABI legacy
FEAT_SB,
FEAT_PREDRES,
RESERVED_FEAT_SSBS, // previously used and now ABI legacy
Expand Down
6 changes: 0 additions & 6 deletions compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_SSBS2);
if (hwcap2 & HWCAP2_MTE)
setCPUFeature(FEAT_MEMTAG2);
if (hwcap2 & HWCAP2_MTE3)
setCPUFeature(FEAT_MEMTAG3);
if (hwcap2 & HWCAP2_SVEPMULL)
setCPUFeature(FEAT_SVE_PMULL128);
if (hwcap2 & HWCAP2_SVEBITPERM)
Expand All @@ -63,8 +61,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_RNG);
if (hwcap2 & HWCAP2_I8MM)
setCPUFeature(FEAT_I8MM);
if (hwcap2 & HWCAP2_EBF16)
setCPUFeature(FEAT_EBF16);
if (hwcap2 & HWCAP2_DGH)
setCPUFeature(FEAT_DGH);
if (hwcap2 & HWCAP2_FRINT)
Expand All @@ -75,8 +71,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
setCPUFeature(FEAT_SVE_F64MM);
if (hwcap2 & HWCAP2_BTI)
setCPUFeature(FEAT_BTI);
if (hwcap2 & HWCAP2_RPRES)
setCPUFeature(FEAT_RPRES);
if (hwcap2 & HWCAP2_WFXT)
setCPUFeature(FEAT_WFXT);
if (hwcap2 & HWCAP2_SME)
Expand Down
6 changes: 3 additions & 3 deletions llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,8 @@ enum CPUFeatures {
FEAT_DGH,
FEAT_I8MM,
FEAT_BF16,
FEAT_EBF16,
FEAT_RPRES,
RESERVED_FEAT_EBF16, // previously used and now ABI legacy
RESERVED_FEAT_RPRES, // previously used and now ABI legacy
FEAT_SVE,
RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy
RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy
Expand All @@ -67,7 +67,7 @@ enum CPUFeatures {
FEAT_SME,
RESERVED_FEAT_MEMTAG, // previously used and now ABI legacy
FEAT_MEMTAG2,
FEAT_MEMTAG3,
RESERVED_FEAT_MEMTAG3, // previously used and now ABI legacy
FEAT_SB,
FEAT_PREDRES,
RESERVED_FEAT_SSBS, // previously used and now ABI legacy
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/AArch64/AArch64FMV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,6 @@ def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>;
def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>;
def : FMVExtension<"dpb2", "FEAT_DPB2", "+ccpp,+ccdp", 200>;
def : FMVExtension<"ebf16", "FEAT_EBF16", "+bf16", 290>;
def : FMVExtension<"f32mm", "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
def : FMVExtension<"f64mm", "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
def : FMVExtension<"fcma", "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
Expand All @@ -61,15 +60,13 @@ def : FMVExtension<"jscvt", "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
def : FMVExtension<"ls64", "FEAT_LS64_ACCDATA", "+ls64", 520>;
def : FMVExtension<"lse", "FEAT_LSE", "+lse", 80>;
def : FMVExtension<"memtag", "FEAT_MEMTAG2", "+mte", 440>;
def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte", 460>;
def : FMVExtension<"mops", "FEAT_MOPS", "+mops", 650>;
def : FMVExtension<"predres", "FEAT_PREDRES", "+predres", 480>;
def : FMVExtension<"rcpc", "FEAT_RCPC", "+rcpc", 230>;
def : FMVExtension<"rcpc2", "FEAT_RCPC2", "+rcpc", 240>;
def : FMVExtension<"rcpc3", "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
def : FMVExtension<"rdm", "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
def : FMVExtension<"rng", "FEAT_RNG", "+rand", 10>;
def : FMVExtension<"rpres", "FEAT_RPRES", "", 300>;
def : FMVExtension<"sb", "FEAT_SB", "+sb", 470>;
def : FMVExtension<"sha2", "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
def : FMVExtension<"sha3", "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
Expand Down

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