emit floating point calyx constant

llvm · May 28, 2024 · 9bb965b · 9bb965b
1 parent 1b6c1bf
commit 9bb965b
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Showing 2 changed files with 53 additions and 3 deletions.
diff --git a/lib/Dialect/Calyx/Export/CalyxEmitter.cpp b/lib/Dialect/Calyx/Export/CalyxEmitter.cpp
@@ -22,6 +22,7 @@
 #include "mlir/Tools/mlir-translate/Translation.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/TypeSwitch.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/FormatVariadic.h"
 
 using namespace circt;
@@ -479,6 +480,17 @@ struct Emitter {
           emitValue(op.getInputs()[0], /*isIndented=*/false);
         })
         .Case<CycleOp>([&](auto op) { emitCycleValue(op); })
+        .Case<calyx::ConstantOp>([&](auto op) {
+          TypedAttr attr = op.getValueAttr();
+          if (auto fltAttr = dyn_cast<FloatAttr>(attr)) {
+            APFloat value = fltAttr.getValue();
+            auto type = cast<FloatType>(fltAttr.getType());
+            double doubleValue = value.convertToDouble();
+            (isIndented ? indent() : os)
+                << std::to_string(value.getSizeInBits(type.getFloatSemantics()))
+                << apostrophe() << "d" << std::to_string(doubleValue);
+          }
+        })
         .Default(
             [&](auto op) { emitOpError(op, "not supported for emission"); });
   }
@@ -637,7 +649,8 @@ void Emitter::emitComponent(ComponentInterface op) {
           .Case<RegisterOp>([&](auto op) { emitRegister(op); })
           .Case<MemoryOp>([&](auto op) { emitMemory(op); })
           .Case<SeqMemoryOp>([&](auto op) { emitSeqMemory(op); })
-          .Case<hw::ConstantOp>([&](auto op) { /*Do nothing*/ })
+          .Case<hw::ConstantOp, calyx::ConstantOp>(
+              [&](auto op) { /*Do nothing*/ })
           .Case<SliceLibOp, PadLibOp, ExtSILibOp>(
               [&](auto op) { emitLibraryPrimTypedByAllPorts(op); })
           .Case<LtLibOp, GtLibOp, EqLibOp, NeqLibOp, GeLibOp, LeLibOp, SltLibOp,
@@ -954,8 +967,8 @@ void Emitter::emitWires(WiresOp op) {
       TypeSwitch<Operation *>(&bodyOp)
           .Case<GroupInterface>([&](auto op) { emitGroup(op); })
           .Case<AssignOp>([&](auto op) { emitAssignment(op); })
-          .Case<hw::ConstantOp, comb::AndOp, comb::OrOp, comb::XorOp, CycleOp>(
-              [&](auto op) { /* Do nothing. */ })
+          .Case<hw::ConstantOp, calyx::ConstantOp, comb::AndOp, comb::OrOp,
+                comb::XorOp, CycleOp>([&](auto op) { /* Do nothing. */ })
           .Default([&](auto op) {
             emitOpError(op, "not supported for emission inside wires section");
           });

diff --git a/test/Dialect/Calyx/emit.mlir b/test/Dialect/Calyx/emit.mlir
@@ -241,3 +241,40 @@ module attributes {calyx.entrypoint = "main"} {
     }
   }
 }
+
+// -----
+
+module attributes {calyx.entrypoint = "main"} {
+  calyx.component @main(%clk: i1 {clk}, %reset: i1 {reset}, %go: i1 {go}) -> (%out0: i32, %out1: f32, %done: i1 {done}) {
+    %c42_i32 = hw.constant 42 : i32
+    %cst = calyx.constant 4.200000e+00 : f32
+    %true = hw.constant true
+    %ret_arg1_reg.in, %ret_arg1_reg.write_en, %ret_arg1_reg.clk, %ret_arg1_reg.reset, %ret_arg1_reg.out, %ret_arg1_reg.done = calyx.register @ret_arg1_reg : f32, i1, i1, i1, f32, i1
+    %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1
+    calyx.wires {
+      calyx.assign %out1 = %ret_arg1_reg.out : f32
+      calyx.assign %out0 = %ret_arg0_reg.out : i32
+
+      // CHECK-LABEL: group ret_assign_0 {
+      // CHECK-NEXT:   ret_arg0_reg.in = 32'd42;
+      // CHECK-NEXT:   ret_arg0_reg.write_en = 1'd1;
+      // CHECK-NEXT:   ret_arg1_reg.in = 32'd4.200000;
+      // CHECK-NEXT:   ret_arg1_reg.write_en = 1'd1;
+      // CHECK-NEXT:   ret_assign_0[done] = (ret_arg1_reg.done & ret_arg0_reg.done) ? 1'd1;
+      // CHECK-NEXT: }
+      calyx.group @ret_assign_0 {
+        calyx.assign %ret_arg0_reg.in = %c42_i32 : i32
+        calyx.assign %ret_arg0_reg.write_en = %true : i1
+        calyx.assign %ret_arg1_reg.in = %cst : f32
+        calyx.assign %ret_arg1_reg.write_en = %true : i1
+        %0 = comb.and %ret_arg1_reg.done, %ret_arg0_reg.done : i1
+        calyx.group_done %0 ? %true : i1
+      }
+    }
+    calyx.control {
+      calyx.seq {
+        calyx.enable @ret_assign_0
+      }
+    }
+  } {toplevel}
+}