[firtool] Can firtool replace special strings in format of assert op?

[Siudya]

Copy these contents to MyModule.fir

FIRRTL version 6.0.0
circuit MyModule :%[[
  {
    "class":"firrtl.transforms.DedupGroupAnnotation",
    "target":"~|MyModule",
    "group":"MyModule"
  }
]]

  public module MyModule :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip a : UInt<1>, b : UInt<1>}

    connect io.b, io.a
    when io.a : 
      node _T = eq(reset, UInt<1>(0h0)) 
      skip
      intrinsic(circt_chisel_ifelsefatal<format = "Assertion failed: {{SimulationTime}}, {{HierarchicalModuleName}}\n", label = "chisel3_builtin">, clock, io.b, _T) 
      when _T :
        skip
        printf(clock, UInt<1>(0h1), "{{SimulationTime}}, {{HierarchicalModuleName}}")

And then run firtool --split-verilog --format fir MyModule.fir -o . with firtool 1.138.0
The assertion and print statement print different strings.

module MyModule(
  input  clock,
         reset,
         io_a,
  output io_b
);

  `ifndef SYNTHESIS
    always @(posedge clock) begin
      automatic logic _GEN = io_a & ~reset;
      if (_GEN & ~io_a) begin
        if (`ASSERT_VERBOSE_COND_)
          $error("Assertion failed: {{SimulationTime}}, {{HierarchicalModuleName}}\n");
        if (`STOP_COND_)
          $fatal;
      end
      if ((`PRINTF_COND_) & _GEN)
        $fwrite(32'h80000002, "%0t, %m", $time);
    end // always @(posedge)
  `endif // not def SYNTHESIS
  assign io_b = io_a;
endmodule

Is it reasonable for firtool to replace the {{SimulationTime}} and {{HierarchicalModuleName}} in the assertion statement?

[seldridge]

Yeah, this is a reasonable feature addition.

[Siudya]

Yeah, this is a reasonable feature addition.

Has it been added to future release plan of firtool?