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[ImportVerilog]: Create variables for function arguments #7829
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LGTM! Thank @Max-astro for your work on this error(#7431).
If you want IR to stay the same when using
You have to implement the |
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Awesome, thanks for implementing this!
If you want to get rid of all the changes in the SV tests, you could do what @hailongSun2000 has suggested and try to delete the variables again if they were not needed. That should make most tests see no real change at all, which may be beneficial? Let me know what you think 😃 I'm also very happy with just landing this!
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Very cool, thanks a lot for doing all this work!
I really appreciate the guidance you provided, it means a lot to me that you took the time to help. |
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So cool!
Can I merge it? @Max-astro |
Sure, I'm glad to hear that. |
Fantastic, thanks for merging @hailongSun2000 and thanks for fixing this bug @Max-astro 🥳! |
Adds shadow variables for SV function arguments.
Fixes: #7431
Adjusts two test cases
test/Conversion/ImportVerilog/basic.sv
andtest/Conversion/ImportVerilog/builtins.sv
Adds two test functions in
test/Conversion/ImportVerilog/builtins.sv
, which will crash in the formercirct-verilog
tool.