[RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU #77631
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…or RISCV and AMDGPU Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen pipeline. This test prematurely stops at the first one, which doesn't cleanup the virtual register map and cause an assertion failure. Ideally we can solve this by teaching `-stop-after` how to stop at the last instance of a Pass, but we're just marking XFAIL for these two targets for now.
arsenm
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Jan 15, 2024
| ; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen | ||
| ; pipeline. This test prematurely stops at the first one, which doesn't cleanup | ||
| ; the virtual register map and cause an assertion failure. Ideally we can solve | ||
| ; this by teaching `-stop-after` how to stop at the last instance of a Pass, |
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You can use -stop-after=passname,1 to skip to the next instance
justinfargnoli
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Jan 28, 2024
…or RISCV and AMDGPU (llvm#77631) Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen pipeline. This test prematurely stops at the first one, which doesn't cleanup the virtual register map and cause an assertion failure. Ideally we can solve this by teaching `-stop-after` how to stop at the last instance of a Pass, but we're just marking XFAIL for these two targets for now.
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Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen pipeline. This test prematurely stops at the first one, which doesn't cleanup the virtual register map and cause an assertion failure. Ideally we can solve this by teaching
-stop-afterhow to stop at the last instance of a Pass, but we're just marking XFAIL for these two targets for now.