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[RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU #77631

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Merged
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Jan 11, 2024
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[RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU #77631

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7 changes: 7 additions & 0 deletions llvm/test/CodeGen/Generic/live-debug-label.ll
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Expand Up @@ -2,6 +2,13 @@
;
; NVPTX produces a different order of the BBs
; XFAIL: target=nvptx{{.*}}
; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
; pipeline. This test prematurely stops at the first one, which doesn't cleanup
; the virtual register map and cause an assertion failure. Ideally we can solve
; this by teaching `-stop-after` how to stop at the last instance of a Pass,
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You can use -stop-after=passname,1 to skip to the next instance

; but we're just marking XFAIL for these two targets for now.
; XFAIL: target=riscv{{.*}}
; XFAIL: target=amdgcn-{{.*}}

; Generated with "clang++ -g -O1 -S -emit-llvm"
;
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