[RISCV][MC] MC layer support for the experimental zalasr extension #79911
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-clang Author: Brendan Sweeney (mehnadnerd) ChangesThis PR implements the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). This PR replaces #69685 because I changed the source branch. Full diff: https://github.com/llvm/llvm-project/pull/79911.diff 13 Files Affected:
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 8f50126f1b36285..3557a6e2304ef0f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -145,6 +145,7 @@
// CHECK-NOT: __riscv_zacas {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
+// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicfiss {{.*$}}
@@ -1120,6 +1121,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
+// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2cfbb10abc8a1c3..fa471bf5e357074 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -228,6 +228,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
+``experimental-zalasr``
+ LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`_.
+
``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `1.0.0-rc2 specification <https://github.com/riscv/riscv-bfloat16/releases/tag/v59042fc71c31a9bcb2f1957621c960ed36fac401>`_.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1ea..0c915d6fb120148 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -194,6 +194,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zaamo", {0, 2}},
{"zacas", {1, 0}},
+ {"zalasr", {0, 1}},
{"zalrsc", {0, 2}},
{"zcmop", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index c822b9c9c624001..f6b5e0280c482b5 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
"'Svpbmt' (Page-Based Memory Types)">;
+def FeatureStdExtZalasr
+ : SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZalasr),
+ "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+
//===----------------------------------------------------------------------===//
// Vendor extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 114329c2c7c5f38..8996ba3bc9f82be 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2144,6 +2144,7 @@ include "RISCVInstrInfoM.td"
// Atomic
include "RISCVInstrInfoA.td"
include "RISCVInstrInfoZa.td"
+include "RISCVInstrInfoZalasr.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
new file mode 100644
index 000000000000000..cb603bb60306295
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the Zalasr (Load-Acquire
+// and Store-Release) extension
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
+ : RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,
+ (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = 0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
+ : RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,
+ (outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
+ opcodestr, "$rs2, $rs1"> {
+ let rd = 0;
+}
+multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {
+ def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
+ def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
+ def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
+ def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+
+let Predicates = [HasStdExtZalasr] in {
+defm LB_AQ : LAQ_r_aq_rl<0b000, "lb">;
+defm LH_AQ : LAQ_r_aq_rl<0b001, "lh">;
+defm LW_AQ : LAQ_r_aq_rl<0b010, "lw">;
+defm SB_RL : SRL_r_aq_rl<0b000, "sb">;
+defm SH_RL : SRL_r_aq_rl<0b001, "sh">;
+defm SW_RL : SRL_r_aq_rl<0b010, "sw">;
+} // Predicates = [HasStdExtZalasr]
+
+let Predicates = [HasStdExtZalasr, IsRV64] in {
+defm LD_AQ : LAQ_r_aq_rl<0b011, "ld">;
+defm SD_RL : SRL_r_aq_rl<0b011, "sd">;
+} // Predicates = [HasStdExtZalasr, IsRV64]
+
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+// Future work: Work out mapping with leading/trailing fences, &c
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index ed1ab5a74f5c4f3..71b109478089758 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -97,6 +97,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -201,6 +202,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
; CHECK: .attribute 4, 16
@@ -298,6 +300,7 @@
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p2"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
@@ -401,6 +404,7 @@
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p2"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
+; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p2"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 5f9a7cabcc768ed..8810ca6781cffd5 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -309,6 +309,9 @@
.attribute arch, "rv32izacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
+.attribute arch, "rv32izalasr0p1"
+# CHECK: attribute 5, "rv32i2p1_zalasr0p1"
+
.attribute arch, "rv32i_xcvalu"
# CHECK: attribute 5, "rv32i2p1_xcvalu1p0"
diff --git a/llvm/test/MC/RISCV/rv32zalasr-invalid.s b/llvm/test/MC/RISCV/rv32zalasr-invalid.s
new file mode 100644
index 000000000000000..3731c85cbc077f4
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalasr-invalid.s
@@ -0,0 +1,40 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
+
+# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+ld.aq a1, (t0)
+
+# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+ld.aqrl a1, (t0)
+
+# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sd.rl a1, (t0)
+
+# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sd.aqrl a1, (t0)
+
+# CHECK: error: unrecognized instruction mnemonic
+lw. a1, (t0)
+
+# CHECK: error: unrecognized instruction mnemonic
+lw.rl t3, 0(t5)
+
+# CHECK: error: unrecognized instruction mnemonic
+lh.rlaq t4, (t6)
+
+# CHECK: error: unrecognized instruction mnemonic
+sb. a1, (t0)
+
+# CHECK: error: unrecognized instruction mnemonic
+sh.aq t3, 0(t5)
+
+# CHECK: error: unrecognized instruction mnemonic
+sh.rlaq t4, (t6)
+
+# CHECK: error: optional integer offset must be 0
+lw.aq zero, 1(a0)
+
+# CHECK: error: optional integer offset must be 0
+sw.rl t1, 2(s0)
+
+# CHECK: error: optional integer offset must be 0
+sb.aqrl sp, 3(s2)
diff --git a/llvm/test/MC/RISCV/rv32zalasr-valid.s b/llvm/test/MC/RISCV/rv32zalasr-valid.s
new file mode 100644
index 000000000000000..fb85fbc00dfea2e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalasr-valid.s
@@ -0,0 +1,70 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: lb.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lb.aq t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lh.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lh.aq t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lw.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lw.aq t1, (a0)
+
+# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lb.aqrl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lh.aqrl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lw.aqrl t1, (a0)
+
+
+# CHECK-ASM-AND-OBJ: sb.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sb.rl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sh.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sh.rl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sw.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sw.rl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sb.aqrl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sh.aqrl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sw.aqrl t1, 0(a0)
diff --git a/llvm/test/MC/RISCV/rv64zalasr-invalid.s b/llvm/test/MC/RISCV/rv64zalasr-invalid.s
new file mode 100644
index 000000000000000..032c0c00882cbf7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalasr-invalid.s
@@ -0,0 +1,28 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
+
+# CHECK: error: unrecognized instruction mnemonic
+lw. a1, (t0)
+
+# CHECK: error: unrecognized instruction mnemonic
+lw.rl t3, 0(t5)
+
+# CHECK: error: unrecognized instruction mnemonic
+lh.rlaq t4, (t6)
+
+# CHECK: error: unrecognized instruction mnemonic
+sb. a1, (t0)
+
+# CHECK: error: unrecognized instruction mnemonic
+sh.aq t3, 0(t5)
+
+# CHECK: error: unrecognized instruction mnemonic
+sh.rlaq t4, (t6)
+
+# CHECK: error: optional integer offset must be 0
+lw.aq zero, 1(a0)
+
+# CHECK: error: optional integer offset must be 0
+sw.rl t1, 2(s0)
+
+# CHECK: error: optional integer offset must be 0
+sb.aqrl sp, 3(s2)
diff --git a/llvm/test/MC/RISCV/rv64zalasr-valid.s b/llvm/test/MC/RISCV/rv64zalasr-valid.s
new file mode 100644
index 000000000000000..9e623ccaaaf887f
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalasr-valid.s
@@ -0,0 +1,91 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
+
+
+# CHECK-ASM-AND-OBJ: lb.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lb.aq t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lh.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lh.aq t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lw.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lw.aq t1, (a0)
+
+# CHECK-ASM-AND-OBJ: ld.aq t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x34]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+ld.aq t1, (a0)
+
+# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lb.aqrl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lh.aqrl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+lw.aqrl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: ld.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x36]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+ld.aqrl t1, 0(a0)
+
+
+# CHECK-ASM-AND-OBJ: sb.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sb.rl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sh.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sh.rl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sw.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sw.rl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sd.rl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sd.rl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sb.aqrl t1, (a0)
+
+# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sh.aqrl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sw.aqrl t1, 0(a0)
+
+# CHECK-ASM-AND-OBJ: sd.aqrl t1, (a0)
+# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3e]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
+sd.aqrl t1, (a0)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index a595526dd24a9a4..b2f2b37e0207866 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -797,6 +797,7 @@ Experimental extensions
zimop 0.1
zaamo 0.2
zacas 1.0
+ zalasr 0.1
zalrsc 0.2
zfbfmin 1.0
zcmop 0.2
|
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Kill stray comments - likely from future change
|
What's the status of Zalasr extension? Is it an official extension now? |
|
I think we need some kind of official documentation to merge this. I went looking to see if I could find mention of this extension in e.g. ARC notes, and didn't find it. @mehnadnerd can you provide some kind of link or reference to some RVI source indicating the status of this proposal? It doesn't need to be near ratified, I'm just worried about the precedent we'd set by accepting an experimental extension with the only reference being an individual person's github. |
|
It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698). It has not yet been approved by the chairs. |
Works for me. I've edited the PR description to include this information so that it ends up in the submit message. I'm about to land this change on @mehnadnerd behalf since he doesn't have commit access. This was requested out of band. |
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…lvm#79911) This PR implements experimental support for the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698), but has not yet been approved by ARC or ratified. See https://github.com/mehnadnerd/riscv-zalasr for draft spec. --------- Co-authored-by: brs <turtwig@utexas.edu> Co-authored-by: Philip Reames <preames@rivosinc.com>
ichaer
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* llvm/main: (500 commits) [docs] Add beginner-focused office hours (llvm#80308) [mlir][sparse] external entry method wrapper for sparse tensors (llvm#80326) [StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (llvm#80242) [libc][stdbit] fix return types (llvm#80337) Revert "[RISCV] Refine cost on Min/Max reduction" (llvm#80340) [TTI]Add support for strided loads/stores. [analyzer][HTMLRewriter] Cache partial rewrite results. (llvm#80220) [flang][openacc][openmp] Use #0 from hlfir.declare value when generating bound ops (llvm#80317) [AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (llvm#74729) [SHT_LLVM_BB_ADDR_MAP][llvm-readobj] Implements llvm-readobj handling for PGOAnalysisMap. (llvm#79520) [libc] add bazel support for most of unistd (llvm#80078) [clang-tidy] Remove enforcement of rule C.48 from cppcoreguidelines-prefer-member-init (llvm#80330) [OpenMP] Fix typo (NFC) (llvm#80332) [BOLT] Enable re-writing of Linux kernel binary (llvm#80228) [BOLT] Adjust section sizes based on file offsets (llvm#80226) [libc] fix stdbit include test when not all entrypoints are available (llvm#80323) [RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (llvm#74114) [RISCV] Add srmcfg CSR from Ssqosid extension. (llvm#79914) [mlir][sparse] add sparsification options to pretty print and debug s… (llvm#80205) [RISCV][MC] MC layer support for the experimental zalasr extension (llvm#79911) ...
agozillon
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…lvm#79911) This PR implements experimental support for the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698), but has not yet been approved by ARC or ratified. See https://github.com/mehnadnerd/riscv-zalasr for draft spec. --------- Co-authored-by: brs <turtwig@utexas.edu> Co-authored-by: Philip Reames <preames@rivosinc.com>
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This PR implements experimental support for the RISC-V Atomic Load-Acquire and Store-Release Extension (Zalasr). It has been approved to be pursued as a fast track extension (https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698), but has not yet been approved by ARC or ratified. See https://github.com/mehnadnerd/riscv-zalasr for draft spec.