[RISCV] Add processor definition for SpacemiT-X60 #94564

sunshaoce · 2024-06-06T04:13:22Z

SpacemiT-X60 is an RVV 1.0 core integrated into the SpacemiT-K1, an 8-core SoC, and it is incorporated into the BPi-F3 development board.

According to the document, relevant information for extensions has been obtained.

BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet
Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh

llvmbot · 2024-06-06T04:13:51Z

@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-clang

Author: Shao-Ce SUN (sunshaoce)

Changes

Spacemit-k1 is a new 8-core CPU that supports RVV 1.0, and it is now integrated into the BPi-F3 development board.

Through ruapo detection, this is the march information of Spacemit-K1:

i
m
a
f
d
c
v
zba
zbb
zbc
zbs
zbkb
zbkc
zfh
zfhmin
zicond
zicsr
zifencei
zmmul
zvfh
zvfhmin
zvl32b
zvl64b
zvl128b
zvl256b

BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet
Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh

Full diff: https://github.com/llvm/llvm-project/pull/94564.diff

3 Files Affected:

(modified) clang/test/Driver/riscv-cpus.c (+12)
(modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+29)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck -check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature" "+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+                                   NoSchedModel,
+                                   [Feature64Bit,
+                                    FeatureStdExtI,
+                                    FeatureStdExtM,
+                                    FeatureStdExtA,
+                                    FeatureStdExtF,
+                                    FeatureStdExtD,
+                                    FeatureStdExtC,
+                                    FeatureStdExtV,
+                                    FeatureStdExtZba,
+                                    FeatureStdExtZbb,
+                                    FeatureStdExtZbc,
+                                    FeatureStdExtZbs,
+                                    FeatureStdExtZbkb,
+                                    FeatureStdExtZbkc,
+                                    FeatureStdExtZfh,
+                                    FeatureStdExtZfhmin,
+                                    FeatureStdExtZicond,
+                                    FeatureStdExtZicsr,
+                                    FeatureStdExtZifencei,
+                                    FeatureStdExtZmmul,
+                                    FeatureStdExtZvfh,
+                                    FeatureStdExtZvfhmin,
+                                    FeatureStdExtZvl32b,
+                                    FeatureStdExtZvl64b,
+                                    FeatureStdExtZvl128b,
+                                    FeatureStdExtZvl256b]>;

llvmbot · 2024-06-06T04:13:51Z

@llvm/pr-subscribers-backend-risc-v

Author: Shao-Ce SUN (sunshaoce)

Changes

Spacemit-k1 is a new 8-core CPU that supports RVV 1.0, and it is now integrated into the BPi-F3 development board.

Through ruapo detection, this is the march information of Spacemit-K1:

i
m
a
f
d
c
v
zba
zbb
zbc
zbs
zbkb
zbkc
zfh
zfhmin
zicond
zicsr
zifencei
zmmul
zvfh
zvfhmin
zvl32b
zvl64b
zvl128b
zvl256b

BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet
Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh

Full diff: https://github.com/llvm/llvm-project/pull/94564.diff

3 Files Affected:

(modified) clang/test/Driver/riscv-cpus.c (+12)
(modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+29)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck -check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature" "+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba" "-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc" "-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+                                   NoSchedModel,
+                                   [Feature64Bit,
+                                    FeatureStdExtI,
+                                    FeatureStdExtM,
+                                    FeatureStdExtA,
+                                    FeatureStdExtF,
+                                    FeatureStdExtD,
+                                    FeatureStdExtC,
+                                    FeatureStdExtV,
+                                    FeatureStdExtZba,
+                                    FeatureStdExtZbb,
+                                    FeatureStdExtZbc,
+                                    FeatureStdExtZbs,
+                                    FeatureStdExtZbkb,
+                                    FeatureStdExtZbkc,
+                                    FeatureStdExtZfh,
+                                    FeatureStdExtZfhmin,
+                                    FeatureStdExtZicond,
+                                    FeatureStdExtZicsr,
+                                    FeatureStdExtZifencei,
+                                    FeatureStdExtZmmul,
+                                    FeatureStdExtZvfh,
+                                    FeatureStdExtZvfhmin,
+                                    FeatureStdExtZvl32b,
+                                    FeatureStdExtZvl64b,
+                                    FeatureStdExtZvl128b,
+                                    FeatureStdExtZvl256b]>;

dtcxzyw · 2024-06-06T04:35:20Z

cc @zengdage

llvm/lib/Target/RISCV/RISCVProcessors.td

wangpc-pp · 2024-06-06T05:23:05Z

Spacemit K1 is the name of the product/SoC or whatever you call it. The processor definitions in the RISCV backend are focusing on the CPU core.
For Spacemit K1, the name of its core should be X60? I don't know……

llvm/lib/Target/RISCV/RISCVProcessors.td

zengdage · 2024-06-06T05:46:07Z

Spacemit K1 is the name of the product/SoC or whatever you call it. The processor definitions in the RISCV backend are focusing on the CPU core. For Spacemit K1, the name of its core should be X60? I don't know……

@sunshaoce Hi, the Spacemit-K1 is the SoC name and the cpu core name is spacemit-x60, so I suggest to use spacemit-x60.

zqb-all · 2024-06-06T05:53:48Z

Spacemit K1 is the name of the product/SoC or whatever you call it. The processor definitions in the RISCV backend are focusing on the CPU core. For Spacemit K1, the name of its core should be X60? I don't know……

Yes，core is x60: https://www.spacemit.com/spacemit-x60-core/

zqb-all · 2024-06-06T08:52:11Z

Need to add zicond, which is not in RVA22S64Features

dtcxzyw

LGTM. But I think it needs a double check by spacemit staffs.

zqb-all · 2024-06-07T01:33:54Z

LGTM. x60 also supports svnapot, and although it seems to have no impact on compiler behavior, I see that it is defined in llvm and is part of RVA23, so it might be worth adding it as well.

wangpc-pp · 2024-06-07T04:19:06Z

The description needs to be revised.

sunshaoce · 2024-06-07T06:13:38Z

All done. Thanks!
Is there anything else that needs to be modified?

llvm/lib/Target/RISCV/RISCVProcessors.td

michaelmaitland · 2024-06-10T17:00:33Z

I want to circle back to a comment made by @asb here:

it's obvious that commercial designs with active support should go in

Since this is in BPi-F3, I think that it constitutes as a commercial design. Will this core have active support on the LLVM side?

preames · 2024-06-10T20:20:30Z

Will this core have active support on the LLVM side?

I can't speak for the vendor, but I'll say that I'm interested in having this supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and having in tree support seems worthwhile. I've ordered one of these myself, and plan on using it for ongoing RISC-V vector development.

sunshaoce · 2024-06-11T03:01:49Z

Added:

Sscofpmf
Sstc
Zvkt
TuneDLenFactor2

Removed:

Zvl32b
Zvl64b
Zvl128b

llvm/lib/Target/RISCV/RISCVProcessors.td

dtcxzyw · 2024-06-11T03:34:02Z

llvm/lib/Target/RISCV/RISCVProcessors.td

+                                        FeatureStdExtZvfhmin,
+                                        FeatureStdExtZvkt,
+                                        FeatureStdExtZvl256b]),
+                                       [TuneDLenFactor2]>;


Does X60 support any macro-fusion?

Since no specific information is publicly available, I think this patch can ignore macro-fusion for now

sunshaoce · 2024-06-18T01:59:40Z

I've tested this patch with spec 2006 int. Everything seems to be running smoothly:

                                  Estimated                       Estimated
                Base     Base       Base        Peak     Peak       Peak
Benchmarks      Ref.   Run Time     Ratio       Ref.   Run Time     Ratio
-------------- ------  ---------  ---------    ------  ---------  ---------
400.perlbench    9770       1899       5.14 *
401.bzip2        9650       3284       2.94 *
403.gcc          8050       1990       4.05 *
429.mcf          9120       5440       1.68 *
445.gobmk       10490       1805       5.81 *
456.hmmer        9330       2585       3.61 *
458.sjeng       12100       2180       5.55 *
462.libquantum  20720        990      20.9  *
464.h264ref     22130       3376       6.56 *
471.omnetpp      6250       3084       2.03 *
473.astar        7020       2613       2.69 *
483.xalancbmk    6900       1873       3.68 *

@preames Could we merge this patch?

michaelmaitland · 2024-06-18T02:46:56Z

Could you explain these numbers? It looks like data in some columns is missing.

sunshaoce · 2024-06-18T03:17:23Z

Could you explain these numbers? It looks like data in some columns is missing.

I only ran the default base metrics once. The geometric mean of this Estimated Base Ratio column can be regarded as the comprehensive score for this item.
Q14. What is the difference between a "base" metric and a "peak" metric?

wangpc-pp

LGTM.

llvm/lib/Target/RISCV/RISCVProcessors.td

topperc · 2024-06-18T07:37:11Z

llvm/lib/Target/RISCV/RISCVProcessors.td

+                                        FeatureStdExtZbkc,
+                                        FeatureStdExtZfh,
+                                        FeatureStdExtZicond,
+                                        FeatureStdExtZmmul,


Please don't list Zmmul separate from M.

Generated "-target-feature" "-zmmul" in clang/test/Driver/riscv-cpus.c.
It seems that M imply Zmmul is not supported yet.
#95070

Generated "-target-feature" "-zmmul" in clang/test/Driver/riscv-cpus.c.
It seems that M imply Zmmul is not supported yet.
#95070

It's not, but what is the benefit to the user to have Zmmul and M both listed?

Addressed. Thanks!

michaelmaitland

LGTM

cyyself · 2024-06-27T02:49:08Z

I have a question: SpacemiT-X60 does not support Zicclsm on Vector, which is the same as K230, as discussed in #88029 . Is the Zicclsm safe here?

SpacemiT-X60 is an RVV 1.0 core integrated into the SpacemiT-K1, an 8-core SoC, and it is incorporated into the BPi-F3 development board. According to the [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), relevant information for extensions has been obtained. BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh

[RISCV] Add processor definition for Spacemit-K1

363e293

sunshaoce requested review from asb, MaskRay, preames, michaelmaitland, dtcxzyw, topperc and wangpc-pp June 6, 2024 04:13

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Jun 6, 2024

dtcxzyw reviewed Jun 6, 2024

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llvm/lib/Target/RISCV/RISCVProcessors.td Outdated Show resolved Hide resolved

fixup! Update RISCVProcessors.td

4c1dccc

wangpc-pp reviewed Jun 6, 2024

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llvm/lib/Target/RISCV/RISCVProcessors.td Outdated Show resolved Hide resolved

fixup! Use name spacemit-x60

620f8cc

sunshaoce changed the title ~~[RISCV] Add processor definition for Spacemit-K1~~ [RISCV] Add processor definition for SpacemiT-X60 Jun 6, 2024

fixup! Add missing extensions

d0a6664

dtcxzyw mentioned this pull request Jun 6, 2024

Fix zbb/zbkb detection nihui/ruapu#111

Merged

dtcxzyw approved these changes Jun 6, 2024

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fixup! Add svnapot ext

eb0d50d

preames requested changes Jun 7, 2024

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llvm/lib/Target/RISCV/RISCVProcessors.td Show resolved Hide resolved

fixup! Adjust extensions info

67a7d08

dtcxzyw reviewed Jun 11, 2024

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fixup! Remove Zvfhmin

4471092

wangpc-pp approved these changes Jun 18, 2024

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wangpc-pp reviewed Jun 18, 2024

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topperc reviewed Jun 18, 2024

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fixup! Remove Zmmul

264bba2

michaelmaitland approved these changes Jun 18, 2024

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sunshaoce merged commit aede380 into llvm:main Jun 18, 2024
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[RISCV] Add processor definition for SpacemiT-X60 #94564

[RISCV] Add processor definition for SpacemiT-X60 #94564

sunshaoce commented Jun 6, 2024 •

edited

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llvmbot commented Jun 6, 2024 •

edited

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cyyself commented Jun 27, 2024

[RISCV] Add processor definition for SpacemiT-X60 #94564

[RISCV] Add processor definition for SpacemiT-X60 #94564

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