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106 Open 337 Closed
106 Open 337 Closed
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Issues list

iverilog Verification Task Fails with Module Not Found error
#1884 opened Nov 4, 2024 by V-Geetha
5
Tileable routing architecture
#1828 opened Sep 10, 2024 by narutozxp
Getting fanin error while trying to use custom pinlocations
#1814 opened Aug 30, 2024 by PradyumnaG
1
Getting an error regarding route_chan_width
#1755 opened Jul 23, 2024 by PradyumnaG
1
Bitstream updates and reconfiguration support in OpenFPGA
#1723 opened Jun 23, 2024 by ohault
1
Assertion '1 == driver_switches.size()
#1710 opened Jun 12, 2024 by kpatinos-intel
1
repacker seems underconstrained and fully constrained would be simpler and easier to work with
#1673 opened May 16, 2024 by rs-dhow
repacker greatly alters one LUT in 2xLUT5 mode of an FLE in some cases when other LUT5 is unused yet configured as a wire-LUT in the .net
#1672 opened May 16, 2024 by rs-dhow
repacker changes internal feedback path to external feedback
#1671 opened May 16, 2024 by rs-dhow
repacker/bitstream generation changes internal block muxing to different IPIN
#1670 opened May 16, 2024 by rs-dhow
bitstream generation changes net routing
#1669 opened May 16, 2024 by rs-dhow
cbx/cby muxes lose inputs if they are on same "index"
#1668 opened May 16, 2024 by rs-dhow
Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH
#1660 opened May 9, 2024 by Gurusatwik
Power analysis report
#1626 opened Apr 16, 2024 by Gurusatwik
1
VPR flat_routing support
#1611 opened Apr 3, 2024 by alaindargelas
2
Repack failure for nets with multiple destinations within a complex block.
#1588 opened Mar 3, 2024 by Crossbomber
1
the output file which contains the position of macros
#1575 opened Feb 20, 2024 by ducminhnguyen123
1
synthesis timing error
#1543 opened Jan 28, 2024 by anudeepdharavathu
Contributor guide link in README is broken
#1534 opened Jan 23, 2024 by DeflateAwning
1
Maintain backward compatibility for concat_pass_wire
#1531 opened Jan 23, 2024 by alaindargelas
Full testbench is not working
#1528 opened Jan 22, 2024 by ducminhnguyen123
9
The config of the server execute openfpga
#1526 opened Jan 19, 2024 by ducminhnguyen123
different area between 10LUTs and 1LUT
#1513 opened Jan 12, 2024 by ducminhnguyen123
5
ql_memory_bank reading bitstream back
#1503 opened Jan 3, 2024 by mustafaarslan0
2
vpr is so slow with large circuit
#1502 opened Jan 3, 2024 by ducminhnguyen123
5
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