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Pull requests: lnis-uofu/OpenFPGA

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Pull requests list

[lib] update vtr to latest flow-scripts openfpga-spice openfpga-tools openfpga-verilog tests VPR
#1896 opened Nov 13, 2024 by tangxifan Loading…
2 of 18 tasks
Bump vtr-verilog-to-routing from 04959b7 to 8178b71 dependencies Pull requests that update a dependency file submodules Pull requests that update Submodules code
#1895 opened Nov 13, 2024 by dependabot bot Loading…
Bump yosys from 0200a76 to 8d0bf3f dependencies Pull requests that update a dependency file submodules Pull requests that update Submodules code
#1894 opened Nov 13, 2024 by dependabot bot Loading…
Add command to generate repack design constraints openfpga-tools
#1889 opened Nov 6, 2024 by fkosar-ql • Draft
8
Add behavior to handle unmapped muxes without constant inputs better documentation openfpga-bitstream openfpga-tools
#1869 opened Oct 17, 2024 by fkosar-ql Loading…
24
Make sure net is valid before setting it as wire LUT output openfpga-tools
#1719 opened Jun 19, 2024 by chungshien Loading…
7
Preserve escaped names openfpga-tools openfpga-verilog
#1589 opened Mar 4, 2024 by alaindargelas Loading…
3
Update FindTBB.cmake
#1238 opened Jun 27, 2023 by yppah56 Loading…
Update FindTBB.cmake
#1161 opened May 10, 2023 by zaidtahirbutt Loading…
2
[WIP] Added option to define subtile in tile_annotation section architecture-description flow-scripts lang-shell tests
#828 opened Oct 5, 2022 by ganeshgore Loading…
5
Arch exploration architecture-description benchmarks cell-library flow-scripts tests
#448 opened Dec 16, 2021 by apond308 • Draft
Timing annotation architecture-description benchmarks flow-scripts tests
#362 opened Jul 22, 2021 by apond308 Loading…
12
Vexriscv BRAM support benchmarks flow-scripts tests
#352 opened Jul 1, 2021 by apond308 Loading…
7
Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines architecture-description flow-scripts
#247 opened Feb 20, 2021 by nachiket Loading…
3 of 16 tasks
9
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