Support IPIN connections from all four sides incoming wires of the GSB

[ganeshgore]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• (Non) Breaking new feature. If so, please provide details in the description section.

To ensure the abutment during physical design, the codebase enforces CBX connections from top and bottom and CBY connections from left and right. However, as the tile-based (CLB+CBX+CBY+SB) methodology is being developed, this constraint doesn't seem mandatory.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

This pull iterates through all 4 sides to find SrcNode connected to any IPIN, to achieve this additional loops are added and some assertions are removed which are available here gg_dev_openfpga on VTR repo

This PR also fixes the GSB writer to print a side for IPIN driving nodes.

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[ganeshgore]

Fixed all failures