Reorganize the pre-processing flags and signal initialization code generation

[tangxifan]

Describe the bug
Currently, pre-processing flags that are auto-generated by OpenFPGA lack a clear organization.

• The Verilog netlist fpga_define.v includes pro-processing flags that are only used by testbenches and simulations.
• The Verilog netlist [define_simulation.v] should include the pro-processing flags that are only used by testbenches and simulations.

An example of content of fpga_defines.v

//-------------------------------------------
//	FPGA Synthesizable Verilog Netlist
//	Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
//	Author: Xifan TANG
//	Organization: University of Utah
//	Date: Sat Nov 21 16:29:01 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

`define ENABLE_TIMING 1

`define ENABLE_SIGNAL_INITIALIZATION 1

`define ICARUS_SIMULATOR 1

In particular, the signal initialization codes are currently embedded in the Verilog modules. These codes are designed to help convergence of HDL simulators when dealing with combinational loops inside FPGA fabrics, which should be generated along with testbenches rather than hardware description.
The outcome is

• The auto-generated Verilog modules are not synthesizable. Users have to manually remove the signal initialization codes when porting the Verilog netlists to synthesis tools, e.g., Design Compiler.
• The signal initialization have to be manually added to testbenches for HDL simulations. This is not a trivial task, which demands a deep understanding on FPGA architecture. The codes should be auto-generated.

Expected behavior
In principle,

• the pre-processing flags for hardware description (which matters if a hardware resource is defined or not) should be placed in a Verilog netlist. The netlist should be generated when execute command write_fabric_verilog. These flags can be included when chip designers implement physical designs.
• the pre-processing flags for testbenches and simulations should be placed in a separated Verilog netlist than those pre-processing flags for hardware description. The netlist should be generated when execute command write_verilog_testbench
• Signal initialization should be removed from auto-generated Verilog modules. These codes should be generated in Verilog testbenches. A pre-processing flag can switch these codes on/off when running simulations.
• Icarus pre-processing flag should be moved to the netlist that contains simulation flags only.

Environment (please complete the following information):

• OS: CentOS, Ubuntu
• Compiler: gcc-8.4
• Version: latest master