[dd, prim_reg_cdc] simplifying condition to help with CCOV #25812
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prim_reg_cdc has a conditional coverage hole in the condition: `src_busy_q && src_ack` since src_ack is only 1 if `src_busy_q`. this is also ensured via the assertion `SrcAckBusyChk_A` Signed-off-by: Antonio Martinez Zambrana <amz@lowrisc.org>
rswarbrick
reviewed
Jan 8, 2025
| if (DstWrReq) begin : gen_wr_req | ||
| assign dst_to_src = src_busy_q && src_ack || src_update && !busy; | ||
| assign dst_to_src = src_ack || src_update && !busy; |
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I realise that you didn't change this (and I actually touched it last!), but I think it would be much easier to read with parens around the second and third terms, so src_ack || (src_update && !busy).
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| // The conditions below assigning to `dst_to_src` had a term originally looking like: | ||
| // `dst_to_src = src_busy_q && src_ack ...` | ||
| // The term above causes missing conditional coverage holes for "01", since src_ack will only be | ||
| // set if src_busy_q is already set (see assertion above SrcAckBusyChk_A) | ||
| // To avoid the conditional coverage hole, `src_busy_q` has been removed from the expression |
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I don't think we need this comment at all. If there's anything more that is worth telling someone, maybe it's worth putting in the commit message.
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prim_reg_cdc has a conditional coverage hole in the condition:
src_busy_q && src_acksince src_ack is only 1 ifsrc_busy_q. this is also ensured via the assertionSrcAckBusyChk_A