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ot_uart
: Add break interrupt and add opt-in mocking of break oversampling
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rivos-eblot
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Please could you describe the breaking system in the UART markdown document since we're using it slightly strangely?
rivos-eblot
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Oct 3, 2025
rivos-eblot
requested changes
Oct 3, 2025
This commit hooks up the QEMU UART RX break event to the `ot_uart` so that the break receive triggers an interrupt. This completely ignores the configured `CTRL.RXBLVL` as we have no notion for "how long" break is being held for. Breaks can be sent to a given CharDev via the QEMU monitor. With the goal of mocking the UART oversampling `VAL` register enough that it can support differentiation between break conditions and not (essentially treating the UART RX like a GPIO strap), we implement logic for outputting either 0x0 or 0xFFFF depending on whether we are "in a break" or not. That is, the `VAL` register will report 16 samples equivalent to the last UART bit received (which is 0 when in a break, and 1 for a stop bit on any valid transmission). We make the assumption here that break is being "held", rather than just being a transient event. This logic is enabled through an `oversample-break` property to make it an opt-in behaviour. To better support flows that use break as a GPIO signal that can be continually asserted, add an additional property that treats incoming break events as a "toggle", such that one break event will cause the UART to enter break until another event tells it to exit break. This is again an opt-in property intended for testing edge-case software that uses UART Break in this way. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
Separate out the UART documentation from the Earlgrey and Darjeeling machine documentation files into its own seperate documentation file (like the `spi_device.md`) and describe in more detail sending break conditions via the QEMU monitor and using the properties to mock break conditions in the oversampled `VAL` register for SW edge cases. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
rivos-eblot
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jwnrt
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This PR hooks up the QEMU UART RX break event to the
ot_uart
so that the break receive triggers an interrupt. This completely ignores the configuredCTRL.RXBLVL
as we have no notion for "how long" break is being held for. Breaks can be sent to a given CharDev via the QEMU monitor.With the goal of mocking the UART oversampling
VAL
register enough that it can support differentiation between break conditions and not (essentially treating the UART RX like a GPIO strap, as Earlgrey's ROM_EXT Rescue 1.0 protocol unfortunately does), we implement logic for outputting either0x0
or0xFFFF
depending on whether we are "in a break" or not. That is, theVAL
register will report 16 samples equivalent to the last UART bit received (which is 0 when in a break, and 1 for a stop bit on any valid transmission). We make the assumption here that break is being "held", rather than just being a transient event. This logic is enabled through anoversample-break
property to make it an opt-in behaviour.To better support the ROM_EXT flows that use break like a strapping, add an additional property that treats incoming break events as a "toggle", such that one break event will cause the UART to enter break until another event tells it to exit break. This is similarly an opt-in property intended for testing edge-case software like ROM_EXT that uses UART Break in this way.