redpitaya: remove default clock

m-labs · Oct 25, 2020 · cb88406 · cb88406
1 parent de8e83b
commit cb88406
Showing 1 changed file with 0 additions and 3 deletions.
diff --git a/migen/build/platforms/redpitaya.py b/migen/build/platforms/redpitaya.py
@@ -102,9 +102,6 @@
 
 
 class Platform(XilinxPlatform):
-    default_clk_name = "clk125"
-    default_clk_period = 8.
-
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io,
             toolchain="vivado")