Fix trailing whitespaces

Related to dotnet/runtime#40887 and dotnet/runtime#40884

mono/mini/cpu-amd64.md

@@ -24,9 +24,9 @@
 #
 # len:number         describe the maximun length in bytes of the instruction
 # 		     number is a positive integer.  If the length is not specified
-#                    it defaults to zero.   But lengths are only checked if the given opcode 
-#                    is encountered during compilation. Some opcodes, like CONV_U4 are 
-#                    transformed into other opcodes in the brg files, so they do not show up 
+#                    it defaults to zero.   But lengths are only checked if the given opcode
+#                    is encountered during compilation. Some opcodes, like CONV_U4 are
+#                    transformed into other opcodes in the brg files, so they do not show up
 #                    during code generation.
 #
 # cost:number        describe how many cycles are needed to complete the instruction (unused)
@@ -270,7 +270,7 @@ float_conv_to_u1: dest:i src1:f len:49
 float_conv_to_i: dest:i src1:f len:49
 float_conv_to_ovf_i: dest:a src1:f len:40
 float_conv_to_ovd_u: dest:a src1:f len:40
-float_mul_ovf: 
+float_mul_ovf:
 float_ceq: dest:i src1:f src2:f len:35
 float_cgt: dest:i src1:f src2:f len:35
 float_cgt_un: dest:i src1:f src2:f len:48
@@ -711,11 +711,11 @@ unpack_highq: dest:x src1:x src2:x len:5 clob:1
 unpack_highps: dest:x src1:x src2:x len:5 clob:1
 unpack_highpd: dest:x src1:x src2:x len:5 clob:1
 
-packw: dest:x src1:x src2:x len:5 clob:1 
-packd: dest:x src1:x src2:x len:5 clob:1 
+packw: dest:x src1:x src2:x len:5 clob:1
+packd: dest:x src1:x src2:x len:5 clob:1
 
-packw_un: dest:x src1:x src2:x len:5 clob:1 
-packd_un: dest:x src1:x src2:x len:6 clob:1 
+packw_un: dest:x src1:x src2:x len:5 clob:1
+packd_un: dest:x src1:x src2:x len:6 clob:1
 
 paddb_sat: dest:x src1:x src2:x len:5 clob:1
 paddb_sat_un: dest:x src1:x src2:x len:5 clob:1
@@ -782,7 +782,7 @@ extract_i2: dest:i src1:x len:13
 extract_u2: dest:i src1:x len:13
 extract_i1: dest:i src1:x len:13
 extract_u1: dest:i src1:x len:13
-extract_r8: dest:f src1:x len:5 
+extract_r8: dest:f src1:x len:5
 
 iconv_to_r4_raw: dest:f src1:i len:10
 
@@ -804,7 +804,7 @@ loadx_aligned_membase: dest:x src1:b len:7
 storex_aligned_membase_reg: dest:b src1:x len:7
 storex_nta_membase_reg: dest:b src1:x len:7
 
-fconv_to_r8_x: dest:x src1:f len:4 
+fconv_to_r8_x: dest:x src1:f len:4
 xconv_r8_to_i4: dest:y src1:x len:7
 
 prefetch_membase: src1:b len:4

mono/mini/cpu-arm.md

@@ -130,8 +130,8 @@ storei2_membase_imm: dest:b len:20
 storei2_membase_reg: dest:b src1:i len:12
 storei4_membase_imm: dest:b len:20
 storei4_membase_reg: dest:b src1:i len:20
-storei8_membase_imm: dest:b 
-storei8_membase_reg: dest:b src1:i 
+storei8_membase_imm: dest:b
+storei8_membase_reg: dest:b src1:i
 storer4_membase_reg: dest:b src1:f len:60
 storer8_membase_reg: dest:b src1:f len:24
 store_memindex: dest:b src1:i src2:i len:4

mono/mini/cpu-mips.md

@@ -118,7 +118,7 @@ storei2_membase_imm: dest:b len:20
 storei2_membase_reg: dest:b src1:i len:20
 storei4_membase_imm: dest:b len:20
 storei4_membase_reg: dest:b src1:i len:20
-storei8_membase_imm: dest:b 
+storei8_membase_imm: dest:b
 storei8_membase_reg: dest:b src1:i len:20
 storer4_membase_reg: dest:b src1:f len:20
 storer8_membase_reg: dest:b src1:f len:20
@@ -156,7 +156,7 @@ add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:20
 # there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules 
+# we simulate them, though (but we need to change the burg rules
 # to allocate a symbolic reg for src2)
 div_imm: dest:i src1:i src2:i len:20
 div_un_imm: dest:i src1:i src2:i len:12
@@ -346,7 +346,7 @@ long_xor_imm: dest:i src1:i clob:1 len:4
 lcompare: src1:i src2:i len:4
 lcompare_imm: src1:i len:12
 
-long_conv_to_r_un: dest:f src1:i src2:i len:37 
+long_conv_to_r_un: dest:f src1:i src2:i len:37
 
 float_beq:    len:16
 float_bne_un: len:16

mono/mini/cpu-ppc.md

@@ -137,7 +137,7 @@ add_imm: dest:i src1:i len:4
 sub_imm: dest:i src1:i len:4
 mul_imm: dest:i src1:i len:4
 # there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules 
+# we simulate them, though (but we need to change the burg rules
 # to allocate a symbolic reg for src2)
 div_imm: dest:i src1:i src2:i len:20
 div_un_imm: dest:i src1:i src2:i len:12
@@ -164,8 +164,8 @@ cond_exc_no: len:8
 cond_exc_c: len:12
 cond_exc_nc: len:8
 long_conv_to_ovf_i: dest:i src1:i src2:i len:32
-long_mul_ovf: 
-long_conv_to_r_un: dest:f src1:i src2:i len:37 
+long_mul_ovf:
+long_conv_to_r_un: dest:f src1:i src2:i len:37
 float_beq: len:8
 float_bne_un: len:8
 float_blt: len:8

mono/mini/cpu-ppc64.md

@@ -141,7 +141,7 @@ add_imm: dest:i src1:i len:4
 sub_imm: dest:i src1:i len:4
 mul_imm: dest:i src1:i len:4
 # there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules 
+# we simulate them, though (but we need to change the burg rules
 # to allocate a symbolic reg for src2)
 div_imm: dest:i src1:i src2:i len:20
 div_un_imm: dest:i src1:i src2:i len:12

mono/mini/cpu-s390x.md

@@ -229,7 +229,7 @@ storei2_membase_reg: dest:b src1:i len:26
 storei4_membase_imm: dest:b len:46
 storei4_membase_reg: dest:b src1:i len:26
 storei8_membase_imm: dest:b len:46
-storei8_membase_reg: dest:b src1:i len:26 
+storei8_membase_reg: dest:b src1:i len:26
 storer4_membase_reg: dest:b src1:f len:28
 storer8_membase_reg: dest:b src1:f len:24
 sub_imm: dest:i src1:i len:18
@@ -332,8 +332,8 @@ long_div: dest:i src1:i src2:i len:12
 long_div_un: dest:i src1:i src2:i len:16
 long_mul: dest:i src1:i src2:i len:12
 long_mul_imm: dest:i src1:i len:20
-long_mul_ovf: dest:i src1:i src2:i len:56 
-long_mul_ovf_un: dest:i src1:i src2:i len:64 
+long_mul_ovf: dest:i src1:i src2:i len:56
+long_mul_ovf_un: dest:i src1:i src2:i len:64
 long_and: dest:i src1:i src2:i len:8
 long_or: dest:i src1:i src2:i len:8
 long_xor: dest:i src1:i src2:i len:8
@@ -368,7 +368,7 @@ long_conv_to_u2: dest:i src1:i len:24
 long_conv_to_u4: dest:i src1:i len:4
 long_conv_to_u8: dest:i src1:i len:4
 long_conv_to_u:  dest:i src1:i len:4
-long_conv_to_r_un: dest:f src1:i len:37 
+long_conv_to_r_un: dest:f src1:i len:37
 
 long_beq: len:8
 long_bge_un: len:8
@@ -399,7 +399,7 @@ int_conv_to_i: dest:i src1:i len:4
 int_conv_to_u1: dest:i src1:i len:10
 int_conv_to_u2: dest:i src1:i len:16
 int_conv_to_u4: dest:i src1:i len:4
-int_conv_to_r_un: dest:f src1:i len:37 
+int_conv_to_r_un: dest:f src1:i len:37
 
 cond_exc_ic: len:8
 cond_exc_ieq: len:8
@@ -431,9 +431,9 @@ vcall2_membase: src1:b len:12 clob:c
 vcall2_reg: src1:i len:8 clob:c
 
 s390_int_add_ovf: len:32 dest:i src1:i src2:i
-s390_int_add_ovf_un: len:32 dest:i src1:i src2:i 
+s390_int_add_ovf_un: len:32 dest:i src1:i src2:i
 s390_int_sub_ovf: len:32 dest:i src1:i src2:i
-s390_int_sub_ovf_un: len:32 dest:i src1:i src2:i 
+s390_int_sub_ovf_un: len:32 dest:i src1:i src2:i
 
 s390_long_add_ovf: dest:i src1:i src2:i len:32
 s390_long_add_ovf_un: dest:i src1:i src2:i len:32

mono/mini/cpu-sparc.md

@@ -263,8 +263,8 @@ long_shl: dest:i src1:i src2:i len:64
 long_shr: dest:i src1:i src2:i len:64
 long_shr_un: dest:i src1:i src2:i len:64
 long_conv_to_ovf_i: dest:i src1:i src2:i len:48
-long_mul_ovf: 
-long_conv_to_r_un: dest:f src1:i src2:i len:64 
+long_mul_ovf:
+long_conv_to_r_un: dest:f src1:i src2:i len:64
 long_shr_imm: dest:i src1:i len:64
 long_shr_un_imm: dest:i src1:i len:64
 long_shl_imm: dest:i src1:i len:64

mono/mini/cpu-x86.md

@@ -25,9 +25,9 @@
 #
 # len:number         describe the maximun length in bytes of the instruction
 # 		     number is a positive integer.  If the length is not specified
-#                    it defaults to zero.   But lengths are only checked if the given opcode 
-#                    is encountered during compilation. Some opcodes, like CONV_U4 are 
-#                    transformed into other opcodes in the brg files, so they do not show up 
+#                    it defaults to zero.   But lengths are only checked if the given opcode
+#                    is encountered during compilation. Some opcodes, like CONV_U4 are
+#                    transformed into other opcodes in the brg files, so they do not show up
 #                    during code generation.
 #
 # cost:number        describe how many cycles are needed to complete the instruction (unused)
@@ -180,8 +180,8 @@ storei2_membase_imm: dest:b len:11
 storei2_membase_reg: dest:b src1:i len:7
 storei4_membase_imm: dest:b len:10
 storei4_membase_reg: dest:b src1:i len:7
-storei8_membase_imm: dest:b 
-storei8_membase_reg: dest:b src1:i 
+storei8_membase_imm: dest:b
+storei8_membase_reg: dest:b src1:i
 storer4_membase_reg: dest:b src1:f len:7
 storer8_membase_reg: dest:b src1:f len:7
 load_membase: dest:i src1:b len:7
@@ -257,7 +257,7 @@ float_conv_to_u1: dest:y src1:f len:39
 float_conv_to_i: dest:i src1:f len:39
 float_conv_to_ovf_i: dest:a src1:f len:30
 float_conv_to_ovd_u: dest:a src1:f len:30
-float_mul_ovf: 
+float_mul_ovf:
 float_ceq: dest:y src1:f src2:f len:25
 float_cgt: dest:y src1:f src2:f len:25
 float_cgt_un: dest:y src1:f src2:f len:37
@@ -425,7 +425,7 @@ cmov_ile_un: dest:i src1:i src2:i len:16 clob:1
 cmov_ilt_un: dest:i src1:i src2:i len:16 clob:1
 
 long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30
-long_conv_to_r8_2: dest:f src1:i src2:i len:14 
+long_conv_to_r8_2: dest:f src1:i src2:i len:14
 long_conv_to_r4_2: dest:f src1:i src2:i len:14
 long_conv_to_r_un_2: dest:f src1:i src2:i len:40
 
@@ -565,11 +565,11 @@ unpack_highq: dest:x src1:x src2:x len:4 clob:1
 unpack_highps: dest:x src1:x src2:x len:3 clob:1
 unpack_highpd: dest:x src1:x src2:x len:4 clob:1
 
-packw: dest:x src1:x src2:x len:4 clob:1 
-packd: dest:x src1:x src2:x len:4 clob:1 
+packw: dest:x src1:x src2:x len:4 clob:1
+packd: dest:x src1:x src2:x len:4 clob:1
 
-packw_un: dest:x src1:x src2:x len:4 clob:1 
-packd_un: dest:x src1:x src2:x len:5 clob:1 
+packw_un: dest:x src1:x src2:x len:4 clob:1
+packd_un: dest:x src1:x src2:x len:5 clob:1
 
 paddb_sat: dest:x src1:x src2:x len:4 clob:1
 paddb_sat_un: dest:x src1:x src2:x len:4 clob:1
@@ -634,7 +634,7 @@ extract_i2: dest:i src1:x len:10
 extract_u2: dest:i src1:x len:10
 extract_i1: dest:i src1:x len:10
 extract_u1: dest:i src1:x len:10
-extract_r8: dest:f src1:x len:8 
+extract_r8: dest:f src1:x len:8
 
 insert_i2: dest:x src1:x src2:i len:5 clob:1
 
@@ -653,7 +653,7 @@ loadx_aligned_membase: dest:x src1:b len:7
 storex_aligned_membase_reg: dest:b src1:x len:7
 storex_nta_membase_reg: dest:b src1:x len:7
 
-fconv_to_r8_x: dest:x src1:f len:14 
+fconv_to_r8_x: dest:x src1:f len:14
 xconv_r8_to_i4: dest:y src1:x len:7
 
 prefetch_membase: src1:b len:4

mono/tests/metadata-verifier/cli-blob-tests.md

@@ -20,7 +20,7 @@ method-def-sig {
 	invalid offset blob.i (table-row (6 0) + 10) + 1 set-byte 0x2E
 	invalid offset blob.i (table-row (6 0) + 10) + 1 set-byte 0x2F
 
-	#upper nimble flags 0x80 is invalid	
+	#upper nimble flags 0x80 is invalid
 	invalid offset blob.i (table-row (6 0) + 10) + 1 set-bit 7
 
 	#sig is too small to decode param count
@@ -89,7 +89,7 @@ method-def-ret-misc {
 method-ref-sig {
 	assembly assembly-with-signatures.exe
 
-	#member ref 0 is has a vararg sig 
+	#member ref 0 is has a vararg sig
 	#member ref 1 don't use vararg
 
 	#2 sentinels
@@ -156,23 +156,23 @@ locals-sig {
 
 	#bad local sig
 	#row 0 has tons of locals
-	#row 1 is int32&, int32 
+	#row 1 is int32&, int32
 	#row 2 is typedref
 
 	#typedref with byref
-	#row 1 is:      cconv pcount(2) byref int32      int32 
+	#row 1 is:      cconv pcount(2) byref int32      int32
 	#row 1 goes to: cconv pcount(2) byref typedbyref int32
 	invalid offset blob.i (table-row (0x11 1)) + 4 set-byte 0x16
 
 	#byref pinned int32
-	#row 1 is:      cconv pcount(2) byref int32  int32 
+	#row 1 is:      cconv pcount(2) byref int32  int32
 	#row 1 goes to: cconv pcount(1) byref pinned int32
 
 	invalid offset blob.i (table-row (0x11 1)) + 2 set-byte 0x01,
 			offset blob.i (table-row (0x11 1)) + 4 set-byte 0x45
 
 	#pinned pinned int32
-	#row 1 is:      cconv pcount(2) byref  int32  int32 
+	#row 1 is:      cconv pcount(2) byref  int32  int32
 	#row 1 goes to: cconv pcount(1) pinned pinned int32
 	#LAMEIMPL MS doesn't care about this
 	valid offset blob.i (table-row (0x11 1)) + 2 set-byte 0x01,
@@ -215,7 +215,7 @@ type-enc {
 	invalid offset blob.i (table-row (0x04 3) + 4) + 3 set-byte 0x16
 
 	#LAMEIMPL MS verifier doesn't catch this one (runtime does)
-	#rank 0 
+	#rank 0
 	invalid offset blob.i (table-row (0x04 3) + 4) + 4 set-byte 0x00
 	#large nsizes
 	invalid offset blob.i (table-row (0x04 3) + 4) + 5 set-byte 0x1F
@@ -240,7 +240,7 @@ type-enc {
 	#fnptr
 	#field 10 is a fnptr
 	#format is: cconv FNPTR cconv pcount ret param* sentinel? param*
-	#LAMESPEC, it lacks the fact that fnptr allows for unmanaged call conv 
+	#LAMESPEC, it lacks the fact that fnptr allows for unmanaged call conv
 	#bad callconv
 	invalid offset blob.i (table-row (0x04 10) + 4) + 3 set-byte 0x88
 
@@ -263,10 +263,10 @@ typespec-sig {
 	#type zero is invalid
 	invalid offset blob.i (table-row (0x1B 0)) + 1 set-byte 0x0
 
-	#LAMESPEC part II, MS allows for cmods on a typespec as well 
+	#LAMESPEC part II, MS allows for cmods on a typespec as well
 	#modreq int32 is invalid
 	#typespec 2 is "modreq int32*" encoded as: PTR CMOD_REQD token INT32
-	#change int to CMOD_REQD token INT32 
+	#change int to CMOD_REQD token INT32
 	valid offset blob.i (table-row (0x1B 2)) + 1 set-byte 0x1f, #CMOD_REQD
 			offset blob.i (table-row (0x1B 2)) + 2 set-byte read.byte (blob.i (table-row (0x1B 2)) + 3), #token
 			offset blob.i (table-row (0x1B 2)) + 3 set-byte 0x08 #int8
@@ -321,7 +321,7 @@ method-header {
 
 	#bad fat header flags
 	#only 0x08 and 0x10 allowed
-	#regular value is 
+	#regular value is
 	invalid offset translate.rva.ind (table-row (0x06 1)) + 0 set-ushort 0x3033 #or 0x20
 	invalid offset translate.rva.ind (table-row (0x06 1)) + 0 set-ushort 0x3053
 	invalid offset translate.rva.ind (table-row (0x06 1)) + 0 set-ushort 0x3093

mono/tests/metadata-verifier/cli-cattr-tests.md

@@ -10,7 +10,7 @@ cattr-without-named-args {
 	#WARNING: peverify don't check custom attributes format beyond the prolog
 	#so it's pointless to use it for this.
 	#We'll take the easy road as well and when verifying the encoded data
-	#assume that the target constructor can be decoded and use the runtime signature.  
+	#assume that the target constructor can be decoded and use the runtime signature.
 
 	#bad size
 	invalid offset blob.i (table-row (0x0C 0) + 4) + 0 set-byte 0x0

mono/tests/metadata-verifier/cli-global-props-tests.md

@@ -24,4 +24,4 @@ fielddef-global-props {
 	badrt offset table-row (4 1) + 2 set-ushort read.ushort (table-row (4 0) + 2), #name
 		  offset table-row (4 1) + 4 set-ushort read.ushort (table-row (4 0) + 4)  #signature
 
-}
+}

mono/tests/metadata-verifier/cli-metadata-tests.md

@@ -54,6 +54,6 @@ cli-metadata-stream-headers {
 	#unkwnown name
 	invalid offset stream-header ( 0 ) + 8 set-byte 0x42
 
-	#duplicate name, change #~ to #US 
+	#duplicate name, change #~ to #US
 	invalid offset stream-header ( 0 ) + 9 set-byte 0x55 , offset stream-header ( 0 ) + 10 set-byte 0x53
-}
+}