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Improvements in block storage and target definitions (#1838)
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@josesimoes
josesimoes authored Mar 1, 2021
1 parent 3d11878 commit f5fc3fc
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Showing 6 changed files with 177 additions and 136 deletions.
52 changes: 33 additions & 19 deletions targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_BlockStorage_Esp32FlashDriver.h
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Expand Up @@ -11,22 +11,36 @@

#include <nanoPAL_BlockStorage.h>


//!< .NanoFramework deploy partition
#define ESP_PARTITION_SUBTYPE_DATA_NANOCLR (esp_partition_subtype_t)0x84
//--//

bool Esp32FlashDriver_InitializeDevice(void*);
bool Esp32FlashDriver_UninitializeDevice(void*);
DeviceBlockInfo* Esp32FlashDriver_GetDeviceInfo(void*);
bool Esp32FlashDriver_Read(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer);
bool Esp32FlashDriver_Write(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite);
bool Esp32FlashDriver_IsBlockErased(void*, ByteAddress blockAddress, unsigned int length);
bool Esp32FlashDriver_EraseBlock(void*, ByteAddress address);
void Esp32FlashDriver_SetPowerState(void*, unsigned int state);
bool Esp32FlashDriver_GetMemoryMappedAddress(void*, unsigned int blockRegionIndex, unsigned int blockRangeIndex, unsigned int* address);

extern const DRAM_ATTR esp_partition_t * g_pFlashDriver_partition;
extern const void * g_esp32_flash_start_ptr;

#endif //_TARGET_ESP32FLASH_DRIVER_H_
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// This is ESP_PARTITION sub type specific to .NET nanoFramework.
// See official docs here:
// https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/partition-tables.html#subtype
//
// We are hijacking subtype 0x84.
// Partitions table must use this SUBTYPE code in the table.
#define ESP_PARTITION_SUBTYPE_DATA_NANOCLR (esp_partition_subtype_t)0x84
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////

bool Esp32FlashDriver_InitializeDevice(void *);
bool Esp32FlashDriver_UninitializeDevice(void *);
DeviceBlockInfo *Esp32FlashDriver_GetDeviceInfo(void *);
bool Esp32FlashDriver_Read(void *, ByteAddress startAddress, unsigned int numBytes, unsigned char *buffer);
bool Esp32FlashDriver_Write(
void *,
ByteAddress startAddress,
unsigned int numBytes,
unsigned char *buffer,
bool readModifyWrite);
bool Esp32FlashDriver_IsBlockErased(void *, ByteAddress blockAddress, unsigned int length);
bool Esp32FlashDriver_EraseBlock(void *, ByteAddress address);
void Esp32FlashDriver_SetPowerState(void *, unsigned int state);
bool Esp32FlashDriver_GetMemoryMappedAddress(
void *,
unsigned int blockRegionIndex,
unsigned int blockRangeIndex,
unsigned int *address);

extern const DRAM_ATTR esp_partition_t *g_pFlashDriver_partition;
extern const void *g_esp32_flash_start_ptr;

#endif //_TARGET_ESP32FLASH_DRIVER_H_
3 changes: 0 additions & 3 deletions targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h
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Expand Up @@ -59,7 +59,4 @@ extern portMUX_TYPE globalLockMutex;
#endif // EVENTS_HEART_BEAT
#endif

extern int HeapBegin;
extern int HeapEnd;

#endif //_TARGET_HAL_H_
207 changes: 118 additions & 89 deletions targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Device_BlockStorage.c
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Expand Up @@ -9,129 +9,158 @@
#include <esp32_os.h>
#include <esp_partition.h>

#include <Target_BlockStorage_Esp32FlashDriver.h>

// the block ranges mirror the partition table
// spliting each partition on it's own block range is required to use memory mapping


const BlockRange BlockRange1[] =
{
// factory
{ BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x010000 nanoCLR
const BlockRange BlockRange1[] = {
// partition: factory (nanoCLR)
{BlockRange_BLOCKTYPE_CODE, 0, 0},
};

const BlockRange BlockRange2[] =
{
// deploy
{ BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 }, // 0x110000 deployment
const BlockRange BlockRange2[] = {
// partition: deploy
{BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0},
};

const BlockRange BlockRange3[] =
{
// config
{ BlockRange_BLOCKTYPE_CONFIG , 0, 0 } // 0x2D0000 config
};
const BlockRange BlockRange3[] = {
// partition: config
{BlockRange_BLOCKTYPE_CONFIG, 0, 0}};

BlockRegionInfo BlockRegions[] =
{
// nanoCLR
// The block regions are defined with 0 as the start address and 0 as total bytes per block.
// At boot time, these are filled in @ FixUpBlockRegionInfo() from the partition table.
// For simplicity, each region is considered to have a single block.

BlockRegionInfo BlockRegions[] = {
// nanoCLR
{
(0), // no attributes for this region
0x010000, // start address for block region
1, // total number of blocks in this region
0x100000, // total number of bytes per block
// no attributes for this region
(0),
// start address for block region
0,
// total number of blocks in this region
1,
// total number of bytes per block
0,
ARRAYSIZE_CONST_EXPR(BlockRange1),
BlockRange1,
},

// Deployment area
// Deployment area
{
(BlockRegionAttribute_MemoryMapped), // this region is memory mapped
0x110000, // start address for block region
1, // total number of blocks in this region
0x70000, // total number of bytes per block
// this region is memory mapped
(BlockRegionAttribute_MemoryMapped),
// start address for block region
0,
// total number of blocks in this region
1,
// total number of bytes per block
0,
ARRAYSIZE_CONST_EXPR(BlockRange2),
BlockRange2,
},

// Config, SPIFS partition
// Config, SPIFS partition
{
(0), // no attributes for this region
0x0, // start address for block region
1, // total number of blocks in this region
0x10000, // total number of bytes per block
// no attributes for this region
(0),
// start address for block region
0,
// total number of blocks in this region
1,
// total number of bytes per block
0,
ARRAYSIZE_CONST_EXPR(BlockRange3),
BlockRange3,
}
};


const DeviceBlockInfo Device_BlockInfo =
{
(0), // ESP32 storage doesn't supports XIP, instead it provides memory mapped read access to SPI storage
1, // UINT32 BytesPerSector
ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions;
(BlockRegionInfo*)BlockRegions // const BlockRegionInfo* pRegions;
};

MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig =
{
{ // BLOCK_CONFIG
}};

const DeviceBlockInfo Device_BlockInfo = {
// ESP32 storage doesn't supports XIP, instead it provides memory mapped read access to SPI storage
(0),
// UINT32 BytesPerSector
1,
// UINT32 NumRegions;
ARRAYSIZE_CONST_EXPR(BlockRegions),
// const BlockRegionInfo* pRegions;
(BlockRegionInfo *)BlockRegions};

MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = {
{
// BLOCK_CONFIG
{
0, // GPIO_PIN Pin;
false, // BOOL ActiveState;
// GPIO_PIN Pin;
0,
// BOOL ActiveState;
false,
},

(DeviceBlockInfo*)&Device_BlockInfo // BlockDeviceinfo
(DeviceBlockInfo *)&Device_BlockInfo // BlockDeviceinfo
},

{ // CPU_MEMORY_CONFIG
0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect;
true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly;
0, // UINT32 CPU_MEMORY_CONFIG::WaitStates;
0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts;
16, // UINT32 CPU_MEMORY_CONFIG::BitWidth;
0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress;
0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes;
0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable
0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead
0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable
// CPU_MEMORY_CONFIG
{
// UINT8 CPU_MEMORY_CONFIG::ChipSelect;
0,
// UINT8 CPU_MEMORY_CONFIG::ReadOnly;
true,
// UINT32 CPU_MEMORY_CONFIG::WaitStates;
0,
// UINT32 CPU_MEMORY_CONFIG::ReleaseCounts;
0,
// UINT32 CPU_MEMORY_CONFIG::BitWidth;
16,
// UINT32 CPU_MEMORY_CONFIG::BaseAddress;
0x08000000,
// UINT32 CPU_MEMORY_CONFIG::SizeInBytes;
0x00200000,
// UINT8 CPU_MEMORY_CONFIG::XREADYEnable
0,
// UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead
0,
// UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable
0,
},

0, // UINT32 ChipProtection;
0, // UINT32 ManufacturerCode;
0, // UINT32 DeviceCode;
// UINT32 ChipProtection;
0,
// UINT32 ManufacturerCode;
0,
// UINT32 DeviceCode;
0,
};

BlockStorageDevice Device_BlockStorage;


BlockStorageDevice Device_BlockStorage;

//
// Fix up Block region info based on current partion layout
//
void FixUpBlockRegionInfo()
{
// nanoCLR
const esp_partition_t * part_nanoClr = esp_partition_find_first(ESP_PARTITION_TYPE_APP, 0, 0);
if (part_nanoClr)
{
BlockRegions[0].Start = part_nanoClr->address;
BlockRegions[0].BytesPerBlock = part_nanoClr->size;
}
// Deployment
const esp_partition_t * part_deploy = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, 0x84, 0);
if (part_deploy)
{
BlockRegions[1].Start = part_deploy->address;
BlockRegions[1].BytesPerBlock = part_deploy->size;
}

// Config
const esp_partition_t * part_config = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, 0);
if (part_config)
{
BlockRegions[2].Start = part_config->address;
BlockRegions[2].BytesPerBlock = part_config->size;
}

// nanoCLR
const esp_partition_t *part_nanoClr =
esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_FACTORY, 0);
if (part_nanoClr)
{
BlockRegions[0].Start = part_nanoClr->address;
BlockRegions[0].BytesPerBlock = part_nanoClr->size;
}

// Deployment
const esp_partition_t *part_deploy =
esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NANOCLR, 0);
if (part_deploy)
{
BlockRegions[1].Start = part_deploy->address;
BlockRegions[1].BytesPerBlock = part_deploy->size;
}

// Config
const esp_partition_t *part_config =
esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, 0);
if (part_config)
{
BlockRegions[2].Start = part_config->address;
BlockRegions[2].BytesPerBlock = part_config->size;
}
}
2 changes: 1 addition & 1 deletion targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL.cpp
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Expand Up @@ -62,7 +62,7 @@ void nanoHAL_Initialize()
HAL_CONTINUATION::InitializeList();
HAL_COMPLETION ::InitializeList();

// Fixup System & Block storage parameters based on Flash chip and parttion layout
// Fixup System & Block storage parameters based on Flash chip and partition layout
FixUpHalSystemConfig();
FixUpBlockRegionInfo();

Expand Down
21 changes: 9 additions & 12 deletions targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.c
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Expand Up @@ -10,23 +10,20 @@

#include <spi_flash.h>

HAL_SYSTEM_CONFIG HalSystemConfig =
{
{ true }, // HAL_DRIVER_CONFIG_HEADER Header;
HAL_SYSTEM_CONFIG HalSystemConfig = {
{true}, // HAL_DRIVER_CONFIG_HEADER Header;

1, //ConvertCOM_DebugHandle(1),
0, //ConvertCOM_DebugHandle(0),
1, // ConvertCOM_DebugHandle(1),
0, // ConvertCOM_DebugHandle(0),
921600,
0, // STDIO = COM2 or COM1

{ RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size },
{ FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size }
};
0, // STDIO = COM2 or COM1

HAL_TARGET_CONFIGURATION g_TargetConfiguration;
{RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size},
{FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}};

HAL_TARGET_CONFIGURATION g_TargetConfiguration;

void FixUpHalSystemConfig()
{
HalSystemConfig.FLASH1.Size = g_rom_flashchip.chip_size;
HalSystemConfig.FLASH1.Size = g_rom_flashchip.chip_size;
}
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