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Incorrect length check for non-static port map actual. Fixes #817
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nickg committed Dec 20, 2023

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1 parent 17daf3f commit 81fb2aa
Showing 5 changed files with 61 additions and 6 deletions.
3 changes: 3 additions & 0 deletions src/jit/jit-core.c
Original file line number Diff line number Diff line change
@@ -554,6 +554,9 @@ static void jit_emit_trace(diag_t *d, const loc_t *loc, object_t *enclosing,
case T_PACK_INST:
diag_trace(d, loc, "Package$$ %s", istr(tree_ident(tree)));
break;
case T_WAVEFORM:
diag_trace(d, loc, "Equivalent process");
break;
default:
diag_trace(d, loc, "$$%s", istr(tree_ident(tree)));
break;
14 changes: 8 additions & 6 deletions src/lower.c
Original file line number Diff line number Diff line change
@@ -11479,8 +11479,8 @@ static void lower_map_signal(lower_unit_t *lu, vcode_reg_t src_reg,
}

static void lower_non_static_actual(lower_unit_t *parent, tree_t port,
type_t type, vcode_reg_t port_reg,
tree_t wave)
tree_t target, type_t type,
vcode_reg_t port_reg, tree_t wave)
{
// Construct the equivalent process according the procedure in LRM 08
// section 6.5.6.3
@@ -11533,15 +11533,15 @@ static void lower_non_static_actual(lower_unit_t *parent, tree_t port,
{ .kind = PART_ALL,
.reg = nets_reg,
.off = VCODE_INVALID_REG,
.target = port },
.target = target },
{ .kind = PART_POP,
.reg = VCODE_INVALID_REG,
.off = VCODE_INVALID_REG,
}
};

target_part_t *ptr = parts;
lower_signal_assign_target(lu, &ptr, port, value_reg, type,
lower_signal_assign_target(lu, &ptr, target, value_reg, tree_type(expr),
zero_time_reg, zero_time_reg);

emit_return(VCODE_INVALID_REG);
@@ -11686,8 +11686,10 @@ static void lower_port_map(lower_unit_t *lu, tree_t block, tree_t map,
lower_map_signal(lu, src_reg, dst_reg, src_type, dst_type,
conv_func, map);
}
else if (tree_kind(value) == T_WAVEFORM)
lower_non_static_actual(lu, port, name_type, port_reg, value);
else if (tree_kind(value) == T_WAVEFORM) {
tree_t name = tree_subkind(map) == P_NAMED ? tree_name(map) : port;
lower_non_static_actual(lu, port, name, name_type, port_reg, value);
}
else if (value_reg != VCODE_INVALID_REG) {
type_t value_type = tree_type(value);
lower_map_signal(lu, value_reg, port_reg, value_type, name_type,
1 change: 1 addition & 0 deletions test/regress/gold/issue817.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
0ms+0: value length 7 does not match target length 8
48 changes: 48 additions & 0 deletions test/regress/issue817.vhd
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
package test_pkg is
type array_of_vectors is array(integer range 0 to 31) of bit_vector(7 downto 0);
end package;

use work.test_pkg.array_of_vectors ;

entity test is
port (
in_a : in array_of_vectors ;
outs : out array_of_vectors
) ;
end entity ;

architecture arch of test is
begin
process(all)
begin
outs(0) <= in_a(0);
end process ;
end architecture ;

use work.test_pkg.array_of_vectors ;

entity issue817 is
end entity ;

architecture arch of issue817 is

signal a : bit;
signal b : bit_vector(7 downto 0);

begin

U_test_a : entity work.test
port map (
in_a(0) => "1111111" & a, -- OK
in_a(1) => "111111" & a, -- Error
outs(0) => b
) ;

tb : process
begin
wait for 100 ns ;
report "Done" ;
std.env.stop ;
end process ;

end architecture ;
1 change: 1 addition & 0 deletions test/regress/testlist.txt
Original file line number Diff line number Diff line change
@@ -912,3 +912,4 @@ elab40 normal,2008
cmdline9 shell,slow
genpack16 normal,2008
issue815 normal,2019
issue817 fail,gold,2008

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