No visible declaration error

[cameronweston]

I'm struggling to find the reason why I'm getting a no visible declaration error during the analysis stage. When trying to compile one file I get the error twice for each component it instantiates.

** Error: no visible declaration for LIBA.INTADCCTRL
     > /mnt/path/ctrl.vhd:136
     |
 136 |   adcCtrl : entity liba.intAdcCtrl
     |   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
** Error: no visible declaration for LIBA.INTERFACE
     > /mnt/path/ctrl.vhd:155
     |
 155 |   Interface_inst : entity liba.Interface
     |   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

I made sure the files were included in the analysis step before analyzing ctrl.vhd. If I look inside the liba folder I can see the files.

LIBA.INTADCCTRL
LIBA.INTADCCTRL-RTL
LIBA.INTERFACE
LIBA.INTERFACE-TB
_NVC_LIB
_index

The command is formatted as such:

nvc --work=liba -L./ -a /mnt/path/Interface.vhd /mnt/path/intAdcCtrl.vhd /mnt/ctrl.vhd

[cameronweston]

Okay I believe I found the issue. If I have a file named the same thing as my library name then I get this error. Here is a simple example.

mylib.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package mylib is
  constant C_CONSTANT : integer := 2;
end package;

cntr.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cntr is
  port (
    clk     : in std_logic;
    rst_l   : in std_logic;
    a       : in std_logic_vector(7 downto 0);
    b       : in std_logic_vector(7 downto 0);
    c       : out std_logic_vector(8 downto 0)
  );
end cntr;

architecture rtl of cntr is
begin
cnt_reg : process (clk, rst_l)
begin
  if rst_l = '0' then
    c <= (others => '0');
  elsif rising_edge(clk) then
    c <= std_logic_vector(unsigned(a) + unsigned(b));
  end if;
end process;
end rtl;

top.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library mylib;
use mylib.mylib.all;  --Comment this out and the error goes away

entity top is
  port (
    clk     : in std_logic;
    rst_l   : in std_logic;
    a       : in std_logic_vector(7 downto 0);
    b       : in std_logic_vector(7 downto 0);
    c       : out std_logic_vector(8 downto 0)
  );
end top;

architecture rtl of top is
begin
  cntr_inst: entity mylib.cntr
   port map(
      clk => clk,
      rst_l => rst_l,
      a => a,
      b => b,
      c => c
  );

end rtl;

Analysis command

$ nvc --work=mylib -L./ -a mylib.vhd cntr.vhd top.vhd 
** Warning: directory mylib already exists and is not an NVC library
** Error: no visible declaration for MYLIB.CNTR
    > top.vhd:29
    |
 29 |   cntr_inst: entity mylib.cntr

Now that I know the issue, I can rename my file so it doesn't match my library name but should this be a bug?

[nickg]

There's a couple of issues here. The first one is that error message is terrible. I've improved it so that it more accurately reports the problem:

** Error: name CNTR not found in package MYLIB
    > test.vhd:54
    |
 54 |   cntr_inst: entity mylib.cntr
    |   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = Note: library MYLIB is hidden

The second issue is that use lib.pack.all shouldn't make the bare package name pack visible (use lib.pack would do that). I noticed ModelSim also has this behaviour and gives a similar error but GHDL doesn't. I checked the LRM carefully and I think GHDL is correct here so I fixed this and the example above should compile with the latest master branch.

[cameronweston]

Thanks for the quick fix!