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IMEM
IMEM
 
 
Modelsim_project
Modelsim_project
 
 
ALU.v
ALU.v
 
 
DMEM.v
DMEM.v
 
 
DMEM.v.bak
DMEM.v.bak
 
 
ImmGen.v
ImmGen.v
 
 
add_4.v
add_4.v
 
 
branch_unit.v
branch_unit.v
 
 
branch_unit.v.bak
branch_unit.v.bak
 
 
decoder.v
decoder.v
 
 
decoder.v.bak
decoder.v.bak
 
 
desktop.ini
desktop.ini
 
 
jump_control.v
jump_control.v
 
 
jump_control.v.bak
jump_control.v.bak
 
 
opt_mux.v
opt_mux.v
 
 
pc.v
pc.v
 
 
pc.v.bak
pc.v.bak
 
 
pc_mux.v
pc_mux.v
 
 
pc_mux.v.bak
pc_mux.v.bak
 
 
readme.md
readme.md
 
 
reg_decoder.v
reg_decoder.v
 
 
regfile32x32.v
regfile32x32.v
 
 
regfile_decoder.v
regfile_decoder.v
 
 
shiftRegD.v
shiftRegD.v
 
 
shiftRegD.v.bak
shiftRegD.v.bak
 
 
shiftRegE.v
shiftRegE.v
 
 
shiftRegF.v
shiftRegF.v
 
 
shiftRegF.v.bak
shiftRegF.v.bak
 
 
shiftRegW.v
shiftRegW.v
 
 
stall_unit.v
stall_unit.v
 
 
stall_unit.v.bak
stall_unit.v.bak
 
 
testbench.v
testbench.v
 
 
top_module.v
top_module.v
 
 
top_module.v.bak
top_module.v.bak
 
 
wbmux.v
wbmux.v
 
 
wbmux.v.bak
wbmux.v.bak
 
 

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This is a course project, a basic implementation of RISC-V Arch. with 5-stages pipeline structure ( there are still some hazard bugs). Verilog source code, assembly test code, Modelsim project file are also included.

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