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o1vm/riscv32im: adding programs for unit tests #2866

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merged 15 commits into from
Dec 11, 2024

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@dannywillems dannywillems commented Dec 5, 2024

The idea of this set of changes is to introduce all the tooling that can be used by the developers working on the riscv32im to test the interpreter.

The set contains targets in the Makefile to compile the RISC-V GNU tool chain and some examples of basic programs written in the RISC-V 32IM ISA.

The test suite could contain actual functional tests, but also tests that should trigger exceptions or detect malicious prover/witness builders. The idea came out after witnessing these kinds of subtle changes.

The test related to o1vm/resources/programs/riscv32im/src/sll.S is commented for now because lui is implemented late in the @svv232 PR train (see #2852), and trying to rebase on top of his branch cause conflicts.

I would suggest having this set of changes on master, and start integrating instructions by instructions, with their corresponding unit test? No strong opinion, but it helps to shape the correctness of the slightly bigger program which is fibonnaci.

@dannywillems dannywillems marked this pull request as draft December 5, 2024 15:59
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codecov bot commented Dec 5, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 72.04%. Comparing base (98e7c35) to head (4c91348).
Report is 19 commits behind head on master.

Additional details and impacted files
@@            Coverage Diff             @@
##           master    #2866      +/-   ##
==========================================
- Coverage   72.04%   72.04%   -0.01%     
==========================================
  Files         257      257              
  Lines       60690    60690              
==========================================
- Hits        43723    43722       -1     
- Misses      16967    16968       +1     

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@dannywillems dannywillems force-pushed the dw/o1vm/riscv32im/unit-test-asm branch 3 times, most recently from 935cd78 to 8e0a808 Compare December 5, 2024 18:16
@dannywillems dannywillems requested a review from svv232 December 5, 2024 18:19
@dannywillems dannywillems marked this pull request as ready for review December 5, 2024 18:19
@dannywillems dannywillems force-pushed the dw/o1vm/riscv32im/unit-test-asm branch 3 times, most recently from 33438ae to 77dc029 Compare December 5, 2024 18:40
@@ -0,0 +1,17 @@
.global _start

exit_success:
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Note: this is the semantics we do define in o1vm/riscv32im. It is not standard.

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Solving conflicts.

@dannywillems dannywillems force-pushed the dw/o1vm/riscv32im/unit-test-asm branch from 77dc029 to 710eaba Compare December 5, 2024 20:04
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Done.

@dannywillems dannywillems requested a review from martyall December 5, 2024 20:17
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Noticed a few things when walking through the o1vm README

o1vm/README.md Outdated Show resolved Hide resolved
o1vm/README.md Outdated Show resolved Hide resolved
o1vm/README.md Outdated Show resolved Hide resolved
Co-authored-by: Martin Allen <31280145+martyall@users.noreply.github.com>
dannywillems and others added 2 commits December 6, 2024 13:44
Co-authored-by: Martin Allen <31280145+martyall@users.noreply.github.com>
Co-authored-by: Martin Allen <31280145+martyall@users.noreply.github.com>
@dannywillems dannywillems merged commit 021346d into master Dec 11, 2024
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@dannywillems dannywillems deleted the dw/o1vm/riscv32im/unit-test-asm branch December 11, 2024 16:11
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2 participants