started tinyfpga_bx.pcf #61
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nextpnr-ice40 -l next.log --hx8k --package ct256 --freq 40 --pcf ../src/servant_1.1.0/data/catzip.pcf --json servant_1.1.0.json --asc servant_1.1.0_next.asc
Info: constrained 'q' to bel 'X3/Y33/io0'
Info: constrained 'i_clk' to bel 'X17/Y33/io0'
Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info: 279 LCs used as LUT4 only
Info: 123 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 130 LCs used as DFF only
Info: Packing carries..
Info: 40 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
ERROR: PLL 'clock_gen.genblk1.pll.genblk1.genblk1.pll' PACKAGEPIN SB_IO 'i_clk$sb_io' is not connected to any PLL BEL
ERROR: Packing design failed.
0 warnings, 2 errors
make: *** [Makefile:23: servant_1.1.0_next.asc] Error 255
ERROR: Failed to build ::servant:1.1.0 : '['make']' exited with an error: 2
icetime -d hx8k -c 40 servant_1.1.0_next.asc
// Reading input .asc file..
// Reading 8k chipdb file..
// Creating timing netlist..
// Timing estimate: 12.22 ns (81.84 MHz)
// Checking 25.00 ns (40.00 MHz) clock constraint: PASSED.
**
less ../src/servant-catzip_pll_1.1.0/pll.vh
* PLL configuration
*
* This Verilog header file was generated automatically
* using the icepll tool from the IceStorm project.
* It is intended for use with FPGA primitives SB_PLL40_CORE,
* SB_PLL40_PAD, SB_PLL40_2_PAD, SB_PLL40_2F_CORE or SB_PLL40_2F_PAD.
* Use at your own risk.
*
* Given input frequency: 100.000 MHz
* Requested output frequency: 40.000 MHz
* Achieved output frequency: 40.000 MHz
*/
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0100), // DIVR = 4
.DIVF(7'b0011111), // DIVF = 31
.DIVQ(3'b100), // DIVQ = 4
.FILTER_RANGE(3'b010) // FILTER_RANGE = 2
Info: Program finished normally.
icepack servant_1.1.0_next.asc servant_1.1.0.bin
INFO: Running
fusesoc run --target=catzip servant from next.log Info: Annotating ports with timing budgets for target frequency 40.00 MHz Info: Max frequency for clock 'wb_clk_$glb_clk': 72.77 MHz (PASS at 40.00 MHz) Info: Program finished normally. icepack servant_1.1.0_next.asc servant_1.1.0.bin
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see mydoc/notes.txt, mydoc/myhelloworld.png mydoc/usbsetup.png |
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description : Catboard iCE40HX8K package CT256 FPGA board |
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initial documentation. |
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Thanks for your contribution. This looks all good if we just drop the mydoc dir. Do you want to do this, or should I do it when I merge? |
o_uart_tx B3 on pmod to be used as q
i_clk C8 100MHz