icetime -d hx8k -c 40 servant_1.1.0_next.asc
// Reading input .asc file..
// Reading 8k chipdb file..
// Creating timing netlist..
// Timing estimate: 12.22 ns (81.84 MHz)
// Checking 25.00 ns (40.00 MHz) clock constraint: PASSED.
**

less ../src/servant-catzip_pll_1.1.0/pll.vh

 * PLL configuration
 *
 * This Verilog header file was generated automatically
 * using the icepll tool from the IceStorm project.
 * It is intended for use with FPGA primitives SB_PLL40_CORE,
 * SB_PLL40_PAD, SB_PLL40_2_PAD, SB_PLL40_2F_CORE or SB_PLL40_2F_PAD.
 * Use at your own risk.
 *
 * Given input frequency:       100.000 MHz
 * Requested output frequency:   40.000 MHz
 * Achieved output frequency:    40.000 MHz
 */

.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0100),         // DIVR =  4
.DIVF(7'b0011111),      // DIVF = 31
.DIVQ(3'b100),          // DIVQ =  4
.FILTER_RANGE(3'b010)   // FILTER_RANGE = 2

Info: Program finished normally.
icepack servant_1.1.0_next.asc servant_1.1.0.bin
INFO: Running

fusesoc run --target=catzip servant
from next.log
Info: Annotating ports with timing budgets for target frequency 40.00 MHz
Info: Max frequency for clock 'wb_clk_$glb_clk': 72.77 MHz (PASS at 40.00 MHz)
Info: Program finished normally.
icepack servant_1.1.0_next.asc servant_1.1.0.bin

description : Catboard iCE40HX8K package CT256 FPGA board