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Unsupported clock edge parameter SAME_EDGE_PIPELINED
#65
opened Mar 2, 2025 by
janrinze
updated Mar 7, 2025
Unrouteable $PACKER_GND_NET sink xx.v:xx.CARRYCASCIN (SITEWIRE/DSP48_X1Y12/CARRYCASCIN)
#64
opened Feb 28, 2025 by
grweiz
updated Feb 28, 2025
Unable to place cell xx, no Bels remaining of type 'LDCE'
#63
opened Feb 28, 2025 by
grweiz
updated Feb 28, 2025
openXC7 - ERROR: Failed to route arc 164 of net 'csi_byte_clk', from SITEWIRE/BUFGCTRL_X0Y23/O to SITEWIRE/SLICE_X3Y114/AFFMUX_OUT
#62
opened Feb 25, 2025 by
harunkovacevic
updated Feb 25, 2025
openXC7 - ERROR: Found IDELAYCTRL but no I/ODELAYs in group default
#60
opened Feb 8, 2025 by
harunkovacevic
updated Feb 8, 2025
openXC7 - no Bels remaining of type 'BUFR'
#56
opened Dec 1, 2024 by
harunkovacevic
updated Dec 3, 2024
openXC7 - no Bels remaining of type 'BUFMR'
#55
opened Nov 19, 2024 by
kerimbavcic
updated Nov 22, 2024
json2dcp: replace deprecated RapidWright API; fix cell placement and routing
#51
opened Oct 30, 2024 by
hansemro
updated Nov 9, 2024
routing hangs for small 8k design without BRAMs
#50
opened Oct 24, 2024 by
mirekez
updated Oct 29, 2024
Limited support for Distributed Memory / LUTRAM
#20
opened Dec 20, 2023 by
hansemro
updated Oct 13, 2024
LUTRAM write occurs on rising edge regardless of IS_WCLK_INVERTED property
#33
opened Jun 29, 2024 by
hansemro
updated Oct 13, 2024
nextpnr cant route design - ERROR: Invalid global constant node 'INT_L_X0Y60/GND_WIRE'
#41
opened Aug 26, 2024 by
mirekez
updated Aug 31, 2024
nextpnr cant route design, Vivado works - ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
#40
opened Aug 26, 2024 by
mirekez
updated Aug 26, 2024
If N polarity pin is used as single clock BUFG, nextpnr gives error ERROR: Invalid global constant node 'INT_L_X0Y109/VCC_WIRE'
#38
opened Aug 22, 2024 by
mirekez
updated Aug 22, 2024
ERROR: Failed to route arc 0 of net '$abc$20823$aiger20822$2149', from SITEWIRE/DSP48_X0Y49/PCOUT23 to SITEWIRE/DSP48_X0Y51/PCIN23
#35
opened Aug 20, 2024 by
mirekez
updated Aug 21, 2024
STA is very rudimentary, down to not even honoring timing constraints, yet alone accounting for clock tree skew
#12
opened Aug 17, 2023 by
chili-chips-ba
updated Jul 25, 2024
oen signal of Tristate outputs is inverted by default in router1
#14
opened Sep 8, 2023 by
hansfbaier
updated Sep 8, 2023
Main analytical placer locks up for designs with high Distributed RAM usage.
#10
opened Aug 17, 2023 by
chili-chips-ba
updated Aug 17, 2023
Error Message by Constraining Positiv OBUFDS Output to negativ Pin Pair
#9
opened Jun 5, 2023 by
FeldmeierMichael
updated Jun 5, 2023
ProTip!
Updated in the last three days: updated:>2025-03-10.