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FCVT.W.S instructions set invalid operation flag of fflags wrongly #727

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salaheddinhetalani opened this issue Sep 27, 2022 · 1 comment
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@salaheddinhetalani
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Issue Description

FCVT.W.S instructions set invalid operation flag "NV" of fflags wrongly.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fcvt.w.s x1, x14, DYN -> fsqrt.s x0, x0, DYN

The instruction fcvt.w.s is decoded at t##0 and executed updating the integer register file at t##1 while setting the invalid flag NV of fflags CSR wrongly. Since the instruction has a dynamic rounding mode, the rounding mode of frm, round down RDN, is used.

Bug_10

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (0),
    .PULP_CLUSTER     (0),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: d0d1c25
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_10.vcd


Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.3_1

@pascalgouedo pascalgouedo added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter labels Nov 9, 2022
@pascalgouedo pascalgouedo added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Mar 23, 2023
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 16, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 16, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 21, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 22, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 29, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Aug 30, 2023
- Fix Underflow flag for MUL and DIV/SQRT operations (openhwgroup#94 openhwgroup#726 openhwgroup#729)
- Fix for Float to Int conversion (openhwgroup#97 openhwgroup#83 openhwgroup#727)
- Fixed unnecessary trailing semicolon (openhwgroup#99)

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
@pascalgouedo
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Resolved with PR #860

@pascalgouedo pascalgouedo added the Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation label Oct 26, 2023
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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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