-
Notifications
You must be signed in to change notification settings - Fork 418
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
FCVT.W.S instructions set invalid operation flag of fflags wrongly #727
Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Comments
pascalgouedo
added
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
labels
Nov 9, 2022
pascalgouedo
added
the
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
label
Mar 23, 2023
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 16, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 16, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 21, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 22, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 29, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo
pushed a commit
to pascalgouedo/cv32e40p
that referenced
this issue
Aug 30, 2023
- Fix Underflow flag for MUL and DIV/SQRT operations (openhwgroup#94 openhwgroup#726 openhwgroup#729) - Fix for Float to Int conversion (openhwgroup#97 openhwgroup#83 openhwgroup#727) - Fixed unnecessary trailing semicolon (openhwgroup#99) Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
Resolved with PR #860 |
pascalgouedo
added
the
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
label
Oct 26, 2023
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Issue Description
FCVT.W.S instructions set invalid operation flag "NV" of fflags wrongly.
Component
Component:RTL
RISC-V Specification
Steps to Reproduce
As shown below, the following sequence of instructions happens:
The instruction
fcvt.w.s
is decoded att##0
and executed updating the integer register file att##1
while setting the invalid flagNV
offflags
CSR wrongly. Since the instruction has a dynamic rounding mode, the rounding mode offrm
, round downRDN
, is used.Top Level Parameters
Git Hash: d0d1c25
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_10.vcd
Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.3_1
The text was updated successfully, but these errors were encountered: