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Custom Xpulp memory instructions update register file wrongly | Simultaneous port writes #742

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salaheddinhetalani opened this issue Nov 28, 2022 · 1 comment
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter PARAM:PULP_ZFINX Issue depends on the PULP_ZFINX parameter Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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Issue Description

If preceded by multicycle F instruction and rd2 is same as rd1, memory RI/I instructions updates the destination register to the address value by the ALU port one cycle later, and thus the loaded data on LSU port is ignored as the ALU port write has a higher priority.

Component

Component:RTL

RISC-V Specification

The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].

The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an f register, it instead accesses the x register with the same number.

Steps to Reproduce

As shown below, the following sequence of instructions happens:

fdiv.s x16, x23, x0, DYN -> cv.ror x1, x0, x4 -> cv.lh.ri x4, x26(x4!) -> jalr x1, x0, 0

The instruction cv.lh.ri is decoded at t##-2 and executed updating the integer register file at t##0 writing x4 by two ports simultaneously. The ALU port writes rs1+rs2 value that is 32'h2000 to x4. At the same time, the LSU port writes the loaded data from memory 32'h400 to x4. Due to the ALU having higher priority, x4 is updated wrongly. This is due to a delay of the ALU port write that is supposed to have happened earlier, but due to having multicycle previous FDIV.S instruction, it got delayed by one cycle. The load instruction accesses the memory at t##-1 setting the memory request. The request is granted at the same cycle and the response from memory is valid at t##0.

Bug_33

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (1),
    .PULP_CLUSTER     (1),
    .FPU              (1),
    .PULP_ZFINX       (1),
    .NUM_MHPMCOUNTERS (1)
)

Git Hash: TBU
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_33.vcd


Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.4_1

@davideschiavone davideschiavone added Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter PARAM:PULP_ZFINX Issue depends on the PULP_ZFINX parameter labels Dec 23, 2022
@pascalgouedo pascalgouedo added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Mar 23, 2023
pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Oct 2, 2023
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
@pascalgouedo
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Resolved with PR #860

pascalgouedo pushed a commit to pascalgouedo/cv32e40p that referenced this issue Oct 10, 2023
…hwgroup#731 and openhwgroup#742 bugs correction.

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
davideschiavone pushed a commit that referenced this issue Oct 10, 2023
* Corrected table name

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>

* Updated SIMD cv.add/cv.sub

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>

* Updated Pipeline details after #723, #652, #731 and #742 bugs correction.

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>

* Formality script improvment

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>

---------

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
@pascalgouedo pascalgouedo added the Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation label Oct 26, 2023
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Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) PARAM:FPU Issue depends on the FPU parameter PARAM:PULP_ZFINX Issue depends on the PULP_ZFINX parameter Status:Resolved Issue has been resolved, but closure is pending on git merge and/or issuer confirmation Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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