Custom Xpulp memory instructions update register file wrongly | Simultaneous port writes #742
Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
PARAM:PULP_ZFINX
Issue depends on the PULP_ZFINX parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Issue Description
If preceded by multicycle F instruction and
rd2
is same asrd1
, memory RI/I instructions updates the destination register to the address value by the ALU port one cycle later, and thus the loaded data on LSU port is ignored as the ALU port write has a higher priority.Component
Component:RTL
RISC-V Specification
Steps to Reproduce
As shown below, the following sequence of instructions happens:
The instruction
cv.lh.ri
is decoded att##-2
and executed updating the integer register file att##0
writingx4
by two ports simultaneously. The ALU port writesrs1+rs2
value that is32'h2000
tox4
. At the same time, the LSU port writes the loaded data from memory32'h400
tox4
. Due to the ALU having higher priority,x4
is updated wrongly. This is due to a delay of the ALU port write that is supposed to have happened earlier, but due to having multicycle previousFDIV.S
instruction, it got delayed by one cycle. The load instruction accesses the memory att##-1
setting the memory request. The request is granted at the same cycle and the response from memory is valid att##0
.Top Level Parameters
Git Hash: TBU
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_33.vcd
Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.4_1
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