Merge from CV32E40X #491
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Merge from CV32E40X #491
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Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
…nd without CLIC. Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Add todo:xif tag on xif related assertions. Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Add assertion a_jalr_stable_target. Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
mcause.minhv only set when taking an exception for a CLIC pointer or mret pointer restart. When jumping due to an mret, mcause.minhv is checked regardless of mcause.mpp. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Clean up truncation warnings in SVA
…its fan-in. The signal clic_ptr_in_wb is used by RVFI but not by the controller. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Fix todo in assertion a_valid_jump.
Signed-off-by: Halfdan Bechmann Dolva <halfdan.bechmann@silabs.com>
Added assert for checking that mepc is always written when mcause.minhv is changed. Refactored some code in controller_fsm. SEC clean. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…ates-aug23 Updates for CLIC spec (august 23)
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Add missing parenthesis in property p_jalr_stable_target
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
…of the LSU. Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
…mevent_we is a single bit in RTL. Signed-off-by: Oivind Ekelund <oivind.ekelund@silabs.com>
Signed-off-by: Halfdan Bechmann Dolva <halfdan.bechmann@silabs.com>
…k_merge-w36.23-1 Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…emoval Remove mscratchcsw register from manual
…te a pointer fetch (ID stage). SEC clean Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…23-2 Removed dependency on mcause.mpp when checking if an mret will genera…
Misc todo fixes in bhv folder
…to change privilege level. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…k_merge-w36.23-1 Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
bhv/cv32e40s_core_log.sv
Outdated
| $display("[cv32e40s_core]: PMP_MSECCFG_RV.rlb = %-1d", PMP_MSECCFG_RV.rlb); | ||
| $display("[cv32e40s_core]: PMP_MSECCFG_RV.mmwp = %-1d", PMP_MSECCFG_RV.mmwp); | ||
| $display("[cv32e40s_core]: PMP_MSECCFG_RV.mml = %-1d", PMP_MSECCFG_RV.mml); | ||
| $display("[cv32e40s_core]: LFSR0_CFG.coeffs = %-1d", LFSR0_CFG.coeffs); |
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LFSR parameters should be printed as hex (0x%8h). %-1d results in a left justified single digit decimal number.
silabs-oivind
suggested changes
Sep 7, 2023
Silabs-ArjanB
requested changes
Sep 7, 2023
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| // Check that register used for JALR target calculation is stable from the jump is taken from ID until the JALR retires from WB. | ||
| // Secure jumps write the link register twice, only checking when the first half (!ex_wb_pipe_i.last_sec_op) is in WB. | ||
| // Excluding rs == x0, as dummies and hints implement actual flops (rf_mem_i[0] would give non-zero value). |
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Add separate assertion for rs == x0
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Added assertion
| @@ -521,11 +520,15 @@ end | |||
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| // Check priviledge level consistency accross the pipeline. | |||
| // The only scenario where priv_lvl_if_q and priv_lvl are allowed to differ is when there's an MRET in the pipe | |||
| // The only scenario where priv_lvl_if_q and priv_lvl are allowed to differ is when there's an MRET or mret pointer in the pipe | |||
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Explain why that is okay and why mret code refers to ID/EX/WB whereas mret_ptr code refers only to EX/WB
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Updated comments
Updated comments and added assertion for jalr with rs1==x0. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Silabs-ArjanB
approved these changes
Sep 7, 2023
Silabs-ArjanB
added
the
Component:RTL
Silabs-ArjanB
approved these changes
Sep 7, 2023
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