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Merge from CV32E40X #491

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merged 34 commits into from
Sep 7, 2023
Merged

Merge from CV32E40X #491

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6982e3e
Removed todo. CLIC assertions implemented in core-v-verif.
silabs-oivind Aug 31, 2023
d492849
Remove CLIC guard around a_single_ptr_fetch. Valid and passing with a…
silabs-oivind Aug 31, 2023
49d5381
Remove assertion a_data_ind_timing. Not applicable for CV32E40X.
silabs-oivind Aug 31, 2023
1075683
Remove TODO. Assertion is correct and passing as it is.
silabs-oivind Aug 31, 2023
951f3f4
Add check for rf_we in assertions checking suppression of csr_en.
silabs-oivind Aug 31, 2023
1f69055
Merge pull request #926 from silabs-oivind/sva_updates_0
Silabs-ArjanB Aug 31, 2023
1a4fe0b
Fix todo in assertion a_valid_jump.
silabs-oivind Aug 31, 2023
4965a65
Fix todos. Update a_kill_if and a_kill_id.
silabs-oivind Aug 31, 2023
c20ae8e
Tag todo with xif
silabs-oivind Aug 31, 2023
cd6e6d5
Updates for CLIC spec (august 23):
silabs-oysteink Aug 31, 2023
eb2074d
Clean up truncation warnings in SVA
silabs-oivind Aug 31, 2023
a9d2ca3
Merge pull request #930 from silabs-oivind/sva_warning_cleanup
Silabs-ArjanB Aug 31, 2023
75b048d
Added 'unused_signals' to controller_fsm and added clic_ptr_in_wb to …
silabs-oysteink Sep 5, 2023
56f3995
Merge pull request #927 from silabs-oivind/sva_updates_1
Silabs-ArjanB Sep 5, 2023
d7e2924
Merge pull request #929 from silabs-oivind/sva_updates_2
Silabs-ArjanB Sep 5, 2023
518b590
Remove mscratchcsw register as it is meant for priv mode change
halfdan-dolva Sep 5, 2023
f528095
Changes after review.
silabs-oysteink Sep 5, 2023
9d71878
Update cv32e40x_controller_fsm.sv
Silabs-ArjanB Sep 5, 2023
71d2f82
Merge pull request #928 from silabs-oysteink/silabs-oysteink_clic-upd…
Silabs-ArjanB Sep 5, 2023
32857d9
Add missing parenthesis in property p_jalr_stable_target
silabs-oivind Sep 5, 2023
9b34c49
Merge pull request #933 from silabs-oivind/fix_sva_error
silabs-oysteink Sep 5, 2023
103ab2c
Fix todo in cv32e40x_core_log
silabs-oivind Sep 6, 2023
0f175bd
Fix todo in cv32e40x_wrapper. Probe lsu_exokay_wb from the core side …
silabs-oivind Sep 6, 2023
6b4f596
Fix todo in cv32e40x_wrapper. Complete cv32e40x_rvfi signal connections.
silabs-oivind Sep 6, 2023
e55d4f5
Remove todo in cv32e40x_wrapper. Current solution works fine, and mhp…
silabs-oivind Sep 6, 2023
84ffbcd
Moved mscratchcsw register into USER section
halfdan-dolva Sep 6, 2023
db52dbe
Merge remote-tracking branch 'openhw_e40x/master' into silabs-oystein…
silabs-oysteink Sep 6, 2023
e12710a
Merge pull request #932 from silabs-halfdan/user_manual_mscratchcsw_r…
Silabs-ArjanB Sep 6, 2023
0237acd
Removed dependency on mcause.mpp when checking if an mret will genera…
silabs-oysteink Sep 6, 2023
128ecb5
Merge pull request #935 from silabs-oysteink/silabs-oysteink-clic-aug…
Silabs-ArjanB Sep 6, 2023
b82c2c8
Merge pull request #934 from silabs-oivind/bhv_todo_fix_0
Silabs-ArjanB Sep 6, 2023
3966245
Updated assertion a_priv_lvl_consistency to also allow mret pointers …
silabs-oysteink Sep 6, 2023
4d0611b
Merge remote-tracking branch 'openhw_e40x/master' into silabs-oystein…
silabs-oysteink Sep 7, 2023
6c02cb8
Updated format for printing LFSR_CFG parameters.
silabs-oysteink Sep 7, 2023
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65 changes: 62 additions & 3 deletions bhv/cv32e40s_core_log.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,27 @@

module cv32e40s_core_log import cv32e40s_pkg::*;
#(
parameter bit ENABLE = 1
// todo: log all parameters
parameter bit ENABLE = 1'b1,
parameter LIB = 0,
parameter rv32_e RV32 = RV32I,
parameter b_ext_e B_EXT = B_NONE,
parameter m_ext_e M_EXT = M,
parameter bit DEBUG = 1,
parameter logic [31:0] DM_REGION_START = 32'hF0000000,
parameter logic [31:0] DM_REGION_END = 32'hF0003FFF,
parameter int DBG_NUM_TRIGGERS = 1,
parameter int PMA_NUM_REGIONS = 0,
parameter pma_cfg_t PMA_CFG[PMA_NUM_REGIONS-1:0] = '{default:PMA_R_DEFAULT},
parameter bit CLIC = 0,
parameter int unsigned CLIC_ID_WIDTH = 5,
parameter int unsigned PMP_GRANULARITY = 0,
parameter int PMP_NUM_REGIONS = 0,
parameter pmpncfg_t PMP_PMPNCFG_RV[PMP_NUM_REGIONS-1:0] = '{default:PMPNCFG_DEFAULT},
parameter logic [31:0] PMP_PMPADDR_RV[PMP_NUM_REGIONS-1:0] = '{default:32'h0},
parameter mseccfg_t PMP_MSECCFG_RV = MSECCFG_DEFAULT,
parameter lfsr_cfg_t LFSR0_CFG = LFSR_CFG_DEFAULT, // Do not use default value for LFSR configuration
parameter lfsr_cfg_t LFSR1_CFG = LFSR_CFG_DEFAULT, // Do not use default value for LFSR configuration
parameter lfsr_cfg_t LFSR2_CFG = LFSR_CFG_DEFAULT // Do not use default value for LFSR configuration
)
(
input logic clk_i,
Expand All @@ -51,7 +70,47 @@ module cv32e40s_core_log import cv32e40s_pkg::*;
`ifndef FORMAL
generate begin
if (ENABLE == 1'b1) begin
// todo: Log top level parameter values
// Log top level parameter values
initial
begin
$display("[cv32e40s_core]: RV32 = %s", RV32.name() );
$display("[cv32e40s_core]: B_EXT = %s", B_EXT.name() );
$display("[cv32e40s_core]: M_EXT = %s", M_EXT.name() );
$display("[cv32e40s_core]: DEBUG = %-1d", DEBUG );
$display("[cv32e40s_core]: DM_REGION_START = 0x%8h", DM_REGION_START );
$display("[cv32e40s_core]: DM_REGION_END = 0x%8h", DM_REGION_END );
$display("[cv32e40s_core]: DBG_NUM_TRIGGERS = %-1d", DBG_NUM_TRIGGERS);
$display("[cv32e40s_core]: PMA_NUM_REGIONS = %-2d", PMA_NUM_REGIONS );
for (int i_pma=0; i_pma<PMA_NUM_REGIONS; i_pma++) begin
$display("[cv32e40s_core]: PMA_CFG[%2d].word_addr_low = 0x%8h", i_pma, PMA_CFG[i_pma].word_addr_low);
$display("[cv32e40s_core]: PMA_CFG[%2d].word_addr_high = 0x%8h", i_pma, PMA_CFG[i_pma].word_addr_high);
$display("[cv32e40s_core]: PMA_CFG[%2d].main = %-1d", i_pma, PMA_CFG[i_pma].main);
$display("[cv32e40s_core]: PMA_CFG[%2d].bufferable = %-1d", i_pma, PMA_CFG[i_pma].bufferable);
$display("[cv32e40s_core]: PMA_CFG[%2d].cacheable = %-1d", i_pma, PMA_CFG[i_pma].cacheable);
$display("[cv32e40s_core]: PMA_CFG[%2d].integrity = %-1d", i_pma, PMA_CFG[i_pma].integrity);
end
$display("[cv32e40s_core]: CLIC = %-1d", CLIC );
$display("[cv32e40s_core]: CLIC_ID_WIDTH = %-2d", CLIC_ID_WIDTH );
$display("[cv32e40s_core]: PMP_GRANULARITY = %-2d", PMP_GRANULARITY );
$display("[cv32e40s_core]: PMP_NUM_REGIONS = %-2d", PMP_NUM_REGIONS );
for (int i_pmp=0; i_pmp<PMP_NUM_REGIONS; i_pmp++) begin
$display("[cv32e40s_core]: PMP_PMPNCFG_RV[%2d].lock = %-1d", i_pmp, PMP_PMPNCFG_RV[i_pmp].lock);
$display("[cv32e40s_core]: PMP_PMPNCFG_RV[%2d].mode = %s", i_pmp, PMP_PMPNCFG_RV[i_pmp].mode.name());
$display("[cv32e40s_core]: PMP_PMPNCFG_RV[%2d].exec = %-1d", i_pmp, PMP_PMPNCFG_RV[i_pmp].exec);
$display("[cv32e40s_core]: PMP_PMPNCFG_RV[%2d].write = %-1d", i_pmp, PMP_PMPNCFG_RV[i_pmp].write);
$display("[cv32e40s_core]: PMP_PMPNCFG_RV[%2d].read = %-1d", i_pmp, PMP_PMPNCFG_RV[i_pmp].read);
$display("[cv32e40s_core]: PMP_PMPADDR_RV[%2d] = 0x%8h", i_pmp, PMP_PMPADDR_RV[i_pmp]);
end
$display("[cv32e40s_core]: PMP_MSECCFG_RV.rlb = %-1d", PMP_MSECCFG_RV.rlb);
$display("[cv32e40s_core]: PMP_MSECCFG_RV.mmwp = %-1d", PMP_MSECCFG_RV.mmwp);
$display("[cv32e40s_core]: PMP_MSECCFG_RV.mml = %-1d", PMP_MSECCFG_RV.mml);
$display("[cv32e40s_core]: LFSR0_CFG.coeffs = 0x%8h", LFSR0_CFG.coeffs);
$display("[cv32e40s_core]: LFSR0_CFG.default_seed = 0x%8h", LFSR0_CFG.default_seed);
$display("[cv32e40s_core]: LFSR1_CFG.coeffs = 0x%8h", LFSR1_CFG.coeffs);
$display("[cv32e40s_core]: LFSR1_CFG.default_seed = 0x%8h", LFSR1_CFG.default_seed);
$display("[cv32e40s_core]: LFSR2_CFG.coeffs = 0x%8h", LFSR2_CFG.coeffs);
$display("[cv32e40s_core]: LFSR2_CFG.default_seed = 0x%8h", LFSR2_CFG.default_seed);
end

// Log illegal instructions
always_ff @(negedge clk_i)
Expand Down
2 changes: 1 addition & 1 deletion bhv/cv32e40s_rvfi_data_obi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ module cv32e40s_rvfi_data_obi import cv32e40s_pkg::*; import cv32e40s_rvfi_pkg::
lsu_data_trans_o = buffer_trans_i;

// Align Memory write data
lsu_data_trans_o.wdata = buffer_trans_wdata_ror;
lsu_data_trans_o.wdata = buffer_trans_wdata_ror[31:0];
end

endmodule
31 changes: 26 additions & 5 deletions bhv/cv32e40s_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -263,7 +263,8 @@ module cv32e40s_wrapper
cv32e40s_controller_fsm_sva
#(.DEBUG(DEBUG),
.CLIC(CLIC),
.CLIC_ID_WIDTH(CLIC_ID_WIDTH))
.CLIC_ID_WIDTH(CLIC_ID_WIDTH),
.RV32(RV32))
controller_fsm_sva (
.lsu_outstanding_cnt (core_i.load_store_unit_i.cnt_q),
.rf_we_wb_i (core_i.wb_stage_i.rf_we_wb_o ),
Expand Down Expand Up @@ -291,6 +292,9 @@ module cv32e40s_wrapper
.ptr_in_if_i (core_i.if_stage_i.ptr_in_if_o),
.instr_req_o (core_i.instr_req_o),
.instr_dbg_o (core_i.instr_dbg_o),
.rf_mem_i (core_i.register_file_wrapper_i.register_file_i.mem),
.alu_jmpr_id_i (core_i.alu_jmpr_id),
.jalr_fw_id_i (core_i.id_stage_i.jalr_fw),
.*);
bind cv32e40s_cs_registers:
core_i.cs_registers_i
Expand Down Expand Up @@ -577,7 +581,26 @@ endgenerate
`endif // `ifndef COREV_ASSERT_OFF

cv32e40s_core_log
#(.ENABLE(CORE_LOG_ENABLE))
#(.ENABLE(CORE_LOG_ENABLE),
.RV32 (RV32),
.B_EXT (B_EXT),
.M_EXT (M_EXT),
.DEBUG (DEBUG),
.DM_REGION_START (DM_REGION_START),
.DM_REGION_END (DM_REGION_END),
.DBG_NUM_TRIGGERS (DBG_NUM_TRIGGERS),
.PMA_NUM_REGIONS (PMA_NUM_REGIONS),
.PMA_CFG (PMA_CFG),
.CLIC (CLIC),
.CLIC_ID_WIDTH (CLIC_ID_WIDTH),
.PMP_GRANULARITY (PMP_GRANULARITY),
.PMP_NUM_REGIONS (PMP_NUM_REGIONS),
.PMP_PMPNCFG_RV (PMP_PMPNCFG_RV),
.PMP_PMPADDR_RV (PMP_PMPADDR_RV),
.PMP_MSECCFG_RV (PMP_MSECCFG_RV),
.LFSR0_CFG (LFSR0_CFG),
.LFSR1_CFG (LFSR1_CFG),
.LFSR2_CFG (LFSR2_CFG))
core_log_i(
.clk_i ( core_i.id_stage_i.clk ),
.ex_wb_pipe_i ( core_i.ex_wb_pipe ),
Expand Down Expand Up @@ -717,7 +740,7 @@ endgenerate
.csr_mcountinhibit_we_i ( core_i.cs_registers_i.mcountinhibit_we ),
.csr_mhpmevent_n_i ( core_i.cs_registers_i.mhpmevent_n ),
.csr_mhpmevent_q_i ( core_i.cs_registers_i.mhpmevent_rdata ),
.csr_mhpmevent_we_i ( {31'h0, core_i.cs_registers_i.mhpmevent_we} << // todo:ok: Add write enable for each register
.csr_mhpmevent_we_i ( {31'h0, core_i.cs_registers_i.mhpmevent_we} <<
core_i.cs_registers_i.csr_waddr[4:0] ),
.csr_mscratch_n_i ( core_i.cs_registers_i.mscratch_n ),
.csr_mscratch_q_i ( core_i.cs_registers_i.mscratch_rdata ),
Expand Down Expand Up @@ -774,8 +797,6 @@ endgenerate
.csr_marchid_i ( core_i.cs_registers_i.marchid_rdata ),
.csr_mhartid_i ( core_i.cs_registers_i.mhartid_rdata ),
.csr_mimpid_i ( core_i.cs_registers_i.mimpid_rdata ),
// TODO Tie relevant signals below to RTL

.csr_mstatush_n_i ( core_i.cs_registers_i.mstatush_n ),
.csr_mstatush_q_i ( core_i.cs_registers_i.mstatush_rdata ),
.csr_mstatush_we_i ( core_i.cs_registers_i.mstatush_we ),
Expand Down
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