Merge pull request #681 from pascalgouedo/dd_pgo

CV32E40Pv2 RISC-V ISA Formal verif reports addition and update of RTL Design tab in RTL Freeze checklist
openhwgroup · Jun 21, 2024 · b4f16e1 · b4f16e1
2 parents f24f9eb + e0e94e5
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diff --git a/...V32E40Pv2/Milestone-data/RTL_v1.8.3/OpenHWGroup_TRL5_for_COREV_RTL_Cheklist-CV32E40P.xlsx b/...V32E40Pv2/Milestone-data/RTL_v1.8.3/OpenHWGroup_TRL5_for_COREV_RTL_Cheklist-CV32E40P.xlsx
diff --git a/...ans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/Reports/RISC-V_ISA_Formal/Bug_Report-v1_8_0.xlsx b/...ans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/Reports/RISC-V_ISA_Formal/Bug_Report-v1_8_0.xlsx
diff --git a/...V32E40Pv2/Milestone-data/RTL_v1.8.3/Reports/RISC-V_ISA_Formal/Property_Status-v1_8_0.xlsx b/...V32E40Pv2/Milestone-data/RTL_v1.8.3/Reports/RISC-V_ISA_Formal/Property_Status-v1_8_0.xlsx