DFU source code? #45

nicolasnoble · 2021-10-19T07:44:18Z

I've been trying to locate the DFU source code of the orange crab for a while now, without success. Is there a documented, reproducible build of it somewhere so we can instantiate the base bootloader?

gregdavill · 2021-10-19T08:35:42Z

The source code is here: https://github.com/gregdavill/foboot/tree/OrangeCrab
The bootloader is based off foboot, I should do a butter job on the documentation around it.

If you checkout the repo with all submodules you should be able to build with the following commnds

$ cd hw
$ python foboot-bitstream.py --platform orangecrab --revision 0.2 --device 25F

Eventually I will move/update the source code into a 'orangecrab-dfu' repo under the orangcrab-fpga org. This is what I've done on the butterstick.

nicolasnoble · 2021-10-19T16:42:47Z

Thanks, appreciated.

nicolasnoble · 2021-10-19T17:01:43Z

Actually, cloning this fails. One of the submodules don't seem to exist, or isn't public:

https://github.com/xobs/lxsocdoc

If taking this submodule out, and running the python script, it'll still complain about it missing, alongside a few more, like https://git.llvm.org/git/compiler-rt/

This looks like there's some case of bitrotting here :-/

lxbuildenv: v2019.8.19.1 (run foboot-bitstream.py --lx-help for help)
lxbuildenv: Missing git submodules -- updating
lxbuildenv: To ignore git issues, re-run with --lx-ignore-git
Submodule 'litex/build/sim/core/modules/ethernet/tapcfg' (https://github.com/enjoy-digital/tapcfg) registered for path 'deps/litex/litex/build/sim/core/modules/ethernet/tapcfg'
Submodule 'litex/soc/cores/cpu/lm32/verilog/submodule' (https://github.com/m-labs/lm32.git) registered for path 'deps/litex/litex/soc/cores/cpu/lm32/verilog/submodule'
Submodule 'litex/soc/cores/cpu/minerva/verilog' (https://github.com/lambdaconcept/minerva) registered for path 'deps/litex/litex/soc/cores/cpu/minerva/verilog'
Submodule 'litex/soc/cores/cpu/mor1kx/verilog' (https://github.com/openrisc/mor1kx.git) registered for path 'deps/litex/litex/soc/cores/cpu/mor1kx/verilog'
Submodule 'litex/soc/cores/cpu/picorv32/verilog' (https://github.com/cliffordwolf/picorv32) registered for path 'deps/litex/litex/soc/cores/cpu/picorv32/verilog'
Submodule 'litex/soc/cores/cpu/rocket/verilog' (https://github.com/enjoy-digital/rocket-litex-verilog) registered for path 'deps/litex/litex/soc/cores/cpu/rocket/verilog'
Submodule 'litex/soc/cores/cpu/vexriscv/verilog' (https://github.com/enjoy-digital/VexRiscv-verilog.git) registered for path 'deps/litex/litex/soc/cores/cpu/vexriscv/verilog'
Submodule 'litex/soc/software/compiler_rt' (https://git.llvm.org/git/compiler-rt) registered for path 'deps/litex/litex/soc/software/compiler_rt'
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/build/sim/core/modules/ethernet/tapcfg'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/lm32/verilog/submodule'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/minerva/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/mor1kx/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/picorv32/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/rocket/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/vexriscv/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/software/compiler_rt'...
fatal: repository 'https://git.llvm.org/git/compiler-rt/' not found
fatal: clone of 'https://git.llvm.org/git/compiler-rt' into submodule path '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/software/compiler_rt' failed
Failed to clone 'litex/soc/software/compiler_rt'. Retry scheduled
Cloning into '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/software/compiler_rt'...
fatal: repository 'https://git.llvm.org/git/compiler-rt/' not found
fatal: clone of 'https://git.llvm.org/git/compiler-rt' into submodule path '/home/pixel/sources/foboot/hw/deps/litex/litex/soc/software/compiler_rt' failed
Failed to clone 'litex/soc/software/compiler_rt' a second time, aborting
Submodule 'test-suite/litex' (https://github.com/enjoy-digital/litex.git) registered for path 'deps/valentyusb/test-suite/litex'
Submodule 'test-suite/usb-test-suite-cocotb-usb' (https://github.com/antmicro/usb-test-suite-cocotb-usb.git) registered for path 'deps/valentyusb/test-suite/usb-test-suite-cocotb-usb'
Submodule 'test-suite/usb-test-suite-testbenches' (https://github.com/antmicro/usb-test-suite-testbenches.git) registered for path 'deps/valentyusb/test-suite/usb-test-suite-testbenches'
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/usb-test-suite-cocotb-usb'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/usb-test-suite-testbenches'...
Submodule path 'deps/valentyusb/test-suite/litex': checked out '3d20442f6ff853e8d522492f74a591472e3579c8'
Submodule 'litex/build/sim/core/modules/ethernet/tapcfg' (https://github.com/enjoy-digital/tapcfg) registered for path 'deps/valentyusb/test-suite/litex/litex/build/sim/core/modules/ethernet/tapcfg'
Submodule 'litex/soc/cores/cpu/lm32/verilog/submodule' (https://github.com/m-labs/lm32.git) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/lm32/verilog/submodule'
Submodule 'litex/soc/cores/cpu/minerva/verilog' (https://github.com/lambdaconcept/minerva) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/minerva/verilog'
Submodule 'litex/soc/cores/cpu/mor1kx/verilog' (https://github.com/openrisc/mor1kx.git) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/mor1kx/verilog'
Submodule 'litex/soc/cores/cpu/picorv32/verilog' (https://github.com/cliffordwolf/picorv32) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/picorv32/verilog'
Submodule 'litex/soc/cores/cpu/rocket/verilog' (https://github.com/enjoy-digital/rocket-litex-verilog) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/rocket/verilog'
Submodule 'litex/soc/cores/cpu/vexriscv/verilog' (https://github.com/enjoy-digital/VexRiscv-verilog.git) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/vexriscv/verilog'
Submodule 'litex/soc/software/compiler_rt' (https://git.llvm.org/git/compiler-rt) registered for path 'deps/valentyusb/test-suite/litex/litex/soc/software/compiler_rt'
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/build/sim/core/modules/ethernet/tapcfg'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/lm32/verilog/submodule'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/minerva/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/mor1kx/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/picorv32/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/rocket/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/cores/cpu/vexriscv/verilog'...
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/software/compiler_rt'...
fatal: repository 'https://git.llvm.org/git/compiler-rt/' not found
fatal: clone of 'https://git.llvm.org/git/compiler-rt' into submodule path '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/software/compiler_rt' failed
Failed to clone 'litex/soc/software/compiler_rt'. Retry scheduled
Cloning into '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/software/compiler_rt'...
fatal: repository 'https://git.llvm.org/git/compiler-rt/' not found
fatal: clone of 'https://git.llvm.org/git/compiler-rt' into submodule path '/home/pixel/sources/foboot/hw/deps/valentyusb/test-suite/litex/litex/soc/software/compiler_rt' failed
Failed to clone 'litex/soc/software/compiler_rt' a second time, aborting
Submodule path 'deps/valentyusb/test-suite/usb-test-suite-cocotb-usb': checked out '1e4c9e5fa4772095d6a0f64f7fd035cfaf273dd0'
Submodule path 'deps/valentyusb/test-suite/usb-test-suite-testbenches': checked out 'd0f9299a970f24abacdf060e6f5bfa7448472399'
Failed to recurse into submodule path 'deps/valentyusb/test-suite/litex'
Failed to recurse into submodule path 'deps/litex'
Failed to recurse into submodule path 'deps/valentyusb'
/home/pixel/sources/foboot/hw/deps/migen/migen/fhdl/visit.py:86: SyntaxWarning: "is" with a literal. Did you mean "=="?
  key=lambda x: -1 if x[0] is "default" else x[0].duid):
/home/pixel/sources/foboot/hw/deps/migen/migen/fhdl/visit.py:191: SyntaxWarning: "is" with a literal. Did you mean "=="?
  key=lambda x: -1 if x[0] is "default" else x[0].duid)}
/home/pixel/sources/foboot/hw/deps/litex/litex/soc/cores/cpu/minerva/core.py:32: SyntaxWarning: "is" with a literal. Did you mean "=="?
  assert variant is "standard", "Unsupported variant %s" % variant
Traceback (most recent call last):
  File "/home/pixel/sources/foboot/hw/foboot-bitstream.py", line 35, in <module>
    import lxsocdoc
ModuleNotFoundError: No module named 'lxsocdoc'

gregdavill · 2021-10-19T23:53:23Z

Whoops, looks like the code there is a bit out of date. And there are some repos that were moved by upstream litex.

I've just fixed those errors, and I can build locally. Let me know if there is any other issues.

nicolasnoble · 2021-10-20T18:05:20Z

Something is still amiss here as far as I can tell, almost as if it's missing files in the repository?

$ git clone --branch OrangeCrab --recursive https://github.com/gregdavill/foboot.git
Cloning into 'foboot'...
remote: Enumerating objects: 3342, done.
[...]
Resolving deltas: 100% (2/2), done.
Submodule path 'hw/deps/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/test/resources/VexRiscvRegressionData': checked out '539398c1481203a51115b5f1228ea961f0ac9bd3'
Submodule path 'hw/deps/pythondata-software-compiler_rt': checked out 'fcb03245613ccf3079cc833a701f13d0beaae09d'
Submodule path 'hw/deps/spibone': checked out '4666e36a6bd63980be7a3555dca32373e29fdf6c'
Submodule path 'hw/deps/valentyusb': checked out '623cdd45b1c5b0af25c3b9050e1fa5a8065c9749'
pixel@genos:~/sources$ cd foboot/
pixel@genos:~/sources/foboot$ git rev-parse HEAD
96ec52b8ef2cf8d000f9fef1acfe50d61ea75fbc
pixel@genos:~/sources/foboot$ cd hw
pixel@genos:~/sources/foboot/hw$ python foboot-bitstream.py --platform orangecrab --revision 0.2 --device 25F
lxbuildenv: v2020.6.1.1 (run foboot-bitstream.py --lx-help for help)
lxbuildenv: Missing git submodules -- updating
lxbuildenv: To ignore git issues, re-run with --lx-ignore-git
Compat: litex.soc.cores.up5kspram is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to litex.soc.cores.ram...........thanks :)
INFO:ECP5PLL:Creating ECP5PLL.
INFO:ECP5PLL:Registering Single Ended ClkIn of 48.00MHz.
INFO:ECP5PLL:Creating ClkOut0 usb_48 of 48.00MHz (+-10000.00ppm).
INFO:ECP5PLL:Creating ClkOut1 usb_12 of 12.00MHz (+-10000.00ppm).
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-10-20 11:02:41)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : LFE5U-25F-8MG285C.
INFO:SoC:System clock: 12.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:ctrl CSR added at Location 0.
INFO:SoCCSRHandler:crg CSR added at Location 1.
INFO:SoCCSRHandler:uart_phy CSR added at Location 2.
INFO:SoCCSRHandler:uart CSR added at Location 3.
INFO:SoCCSRHandler:identifier_mem CSR added at Location 4.
INFO:SoCCSRHandler:timer0 CSR added at Location 5.
INFO:SoCCSRHandler:cpu_or_bridge CSR added at Location 8.
INFO:SoCCSRHandler:usb CSR added at Location 9.
INFO:SoCCSRHandler:picorvspi CSR added at Location 10.
INFO:SoCCSRHandler:touch CSR added at Location 11.
INFO:SoCCSRHandler:reboot CSR added at Location 12.
INFO:SoCCSRHandler:rgb CSR added at Location 13.
INFO:SoCCSRHandler:version CSR added at Location 14.
INFO:SoCCSRHandler:lxspi CSR added at Location 15.
INFO:SoCCSRHandler:messible CSR added at Location 16.
INFO:SoCCSRHandler:button CSR added at Location 17.
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (16)
- ctrl           : 0
- crg            : 1
- uart_phy       : 2
- uart           : 3
- identifier_mem : 4
- timer0         : 5
- cpu_or_bridge  : 8
- usb            : 9
- picorvspi      : 10
- touch          : 11
- reboot         : 12
- rgb            : 13
- version        : 14
- lxspi          : 15
- messible       : 16
- button         : 17
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
INFO:SoC:CPU overriding sram mapping from 0x10000000 to 0x10000000.
INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
INFO:SoC:CPU overriding csr mapping from 0xe0000000 to 0xf0000000.
INFO:SoC:CPU overriding vexriscv_debug mapping from 0xf00f0000 to 0xf00f0000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCIRQHandler:timer0 IRQ added at Location 2.
INFO:SoCIRQHandler:usb IRQ added at Location 3.
INFO:SoCIRQHandler:timer0 IRQ added at Location 2.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoCBusHandler:spiflash Region added at Origin: 0x20000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:spiflash added as Bus Slave.
INFO:ECP5PLL:Config:
clki_div   : 1
clkfb      : 2
clko0_freq : 48.00MHz
clko0_div  : 9
clko0_phase: 0.00°
clko1_freq : 12.00MHz
clko1_div  : 36
clko1_phase: 0.00°
clko2_div  : 1
vco        : 432.00MHz
clkfb_div  : 9
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
sram                : Origin: 0x10000000, Size: 0x00004000, Mode: RW, Cached: True Linker: False
spiflash            : Origin: 0x20000000, Size: 0x01000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (4)
- sram
- rom
- spiflash
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (16)
- ctrl           : 0
- crg            : 1
- uart_phy       : 2
- uart           : 3
- identifier_mem : 4
- timer0         : 5
- cpu_or_bridge  : 8
- usb            : 9
- picorvspi      : 10
- touch          : 11
- reboot         : 12
- rgb            : 13
- version        : 14
- lxspi          : 15
- messible       : 16
- button         : 17
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- timer0 : 2
- usb    : 3
INFO:SoC:--------------------------------------------------------------------------------
make: *** /home/pixel/sources/foboot/hw/build/software/bios: No such file or directory.  Stop.
Traceback (most recent call last):
  File "/home/pixel/sources/foboot/hw/foboot-bitstream.py", line 361, in <module>
    main()
  File "/home/pixel/sources/foboot/hw/foboot-bitstream.py", line 348, in main
    builder._generate_rom_software()
  File "/home/pixel/sources/foboot/hw/deps/litex/litex/soc/integration/builder.py", line 263, in _generate_rom_software
    subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
  File "/usr/lib/python3.9/subprocess.py", line 373, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/home/pixel/sources/foboot/hw/build/software/bios', '-f', '/home/pixel/sources/foboot/sw/Makefile']' returned non-zero exit status 2.

gregdavill · 2021-10-20T22:33:28Z

There seems to be a broken submodule that I'd added but then later removed. It's not currently required since we don't build the LiteX BIOS

git-dep: checking if "/tmp/foboot/hw/deps/pythondata-software-picolibc" requires updating (depth: 1)...
git-dep: subdirectory /tmp/foboot/hw/deps/pythondata-software-picolibc does not exist, so starting update

We have to do some tricks to avoid building and embedding the standard LiteX BIOS firmware. Instead we want to build our own custom firmware. I missed a step which creates the directory structure for the firmware before it builds. Try the latest commit gregdavill/foboot@ab25c15

gregdavill · 2021-10-29T01:55:41Z

Were you able to get the bootloader to build?

nicolasnoble · 2021-10-29T02:33:13Z

No, the toolchain seems to be problematic. It's failing to find basic libc-style headers like stdint.h or string.h. I am using ubuntu with the compiler package found there.

…

On Thu, Oct 28, 2021 at 6:55 PM Gregory Davill ***@***.***> wrote: Were you able to get the bootloader to build? — You are receiving this because you modified the open/close state. Reply to this email directly, view it on GitHub <#45 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABXRXJSHSO3SN7AQAITY3CTUJH5KPANCNFSM5GIOFE3A> .

gregdavill · 2021-10-29T02:38:32Z

Interesting. I've not used the built-in riscv-gcc. Is that this package? gcc-riscv64-unknown-elf
I've been using this one: https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases, and it's what I use on the CI LiteX builds.

shenki · 2021-11-29T08:52:04Z

Litex spits out this warning:

Compat: litex.soc.cores.up5kspram is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to litex.soc.cores.ram...........thanks :)

It can be avoided with this change: gregdavill/foboot#7

When building with the system compiler on Debian (which is going to be similar to @nicolasnoble's setup on Ubuntu), I get:

make: Entering directory '/home/joel/dev/fpgas/oc/foboot/hw/build/software/bios'
CC ../../../../sw/src/dfu.c dfu.o
../../../../sw/src/dfu.c:25:10: fatal error: string.h: No such file or directory
#include <string.h>
^~~~~~~~~~

I think this is because the compiler doesn't have a libc by default (the 'elf' in riscv64-unknown-elf-gcc). We can specify one with specs=picolibc.specs (@keith-packard taught me this in https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=979542).

I suspect Greg's build works because the xpack-dev-tools is built with newlib.

I hacked around and got an image to build. The first step was adding -specs=picolibc.spec. This then broke linking:

/usr/lib/riscv64-unknown-elf/bin/ld:../../../../sw/ld/linker.ld:29: nonconstant expression for load base
collect2: error: ld returned 1 exit status

This is because the spec file will include a generic linker script if -T is not defined. This breaks the custom linker script we have, so we can fix that by specifying the linker script with -T to GCC instead of -Wl,--script (-Wl,-T doesn't work either, to my surprise).

I've made some commits with these fixes. With this I can flash the bitstream to the application area of my OC 85F, and after hitting the button, it enumerates with the new firmware (and I can use it to re-flash too):

[14755.416644] usb 1-1: new full-speed USB device number 36 using xhci_hcd
[14755.569112] usb 1-1: New USB device found, idVendor=1209, idProduct=5af0, bcdDevice= 1.01
[14755.569120] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[14755.569122] usb 1-1: Product: OrangeCrab r0.2 DFU Bootloader v3.1-13-g113c4fdef6a9
[14755.569125] usb 1-1: Manufacturer: GsD

gregdavill/foboot#8

mcleinn · 2021-12-09T17:18:32Z

As adding -specs=picolibc.spec was mentioned: I just built with the same commands under Windows 10 / MSys2 x64, and got
[...]
CC ../../../../sw/src/dfu.c dfu.o
riscv64-unknown-elf-gcc.exe: fatal error: cannot read spec file 'picolibc.specs: No such file or directory
compilation terminated.
[...]
I had to remove the reference to picolibc.spec in the sw-folder Makefile to move on

gregdavill · 2021-12-09T23:56:07Z

A better solution IMO to this would be to port over a newer bootloader that I developed for the ButterStick, Which also builds using upstream litex which builds picolibc as one of the build steps.

keith-packard · 2021-12-13T05:52:42Z

As adding -specs=picolibc.spec was mentioned: I just built with the same commands under Windows 10 / MSys2 x64, and got [...] CC ../../../../sw/src/dfu.c dfu.o riscv64-unknown-elf-gcc.exe: fatal error: cannot read spec file 'picolibc.specs: No such file or directory compilation terminated. [...] I had to remove the reference to picolibc.spec in the sw-folder Makefile to move on

You can build picolibc for windows; I haven't tested it recently, but it worked the last time I messed with the build scripts. With that, you'd be able to use --specs=picolibc.specs there as well.

suarezvictor · 2024-06-14T14:18:29Z

A better solution IMO to this would be to port over a newer bootloader that I developed for the ButterStick, Which also builds using upstream litex which builds picolibc as one of the build steps.

Hi, what's the status of this? I have the 0.1 board and the following command generated a bitstream that didn't work

$ cd hw
$ python foboot-bitstream.py --platform orangecrab --revision 0.1 --device 25F

nicolasnoble closed this as completed Oct 19, 2021

nicolasnoble reopened this Oct 19, 2021

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DFU source code? #45

DFU source code? #45

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DFU source code? #45

DFU source code? #45

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