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SDF sim WIP
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@alaindargelas
alaindargelas committed Aug 28, 2024
1 parent a193fab commit 3e3d96b
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Showing 3 changed files with 73 additions and 10 deletions.
15 changes: 11 additions & 4 deletions src/Compiler/Compiler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -946,7 +946,8 @@ bool Compiler::RegisterCommands(TclInterpreter* interp, bool batchMode) {
sim_tool = sim;
sim_tool_valid = true;
} else if (arg == "rtl" || arg == "gate" || arg == "pnr" ||
arg == "bitstream_fd" || arg == "bitstream_bd") {
arg == "timed_pnr" || arg == "bitstream_fd" ||
arg == "bitstream_bd") {
sim_type = arg;
} else if (arg == "clean") {
clean = true;
Expand Down Expand Up @@ -978,9 +979,12 @@ bool Compiler::RegisterCommands(TclInterpreter* interp, bool batchMode) {
} else if (sim_type == "gate") {
status = compiler->GetSimulator()->Simulate(
Simulator::SimulationType::Gate, sim_tool, wave_file);
} else if (sim_type == "pnr") {
} else if (sim_type == "pnr" || sim_type == "timed_pnr") {
compiler->GetSimulator()->SetTimedSimulation(
(sim_type == "timed_pnr"));
status = compiler->GetSimulator()->Simulate(
Simulator::SimulationType::PNR, sim_tool, wave_file);

} else if (sim_type == "bitstream_fd") {
status = compiler->GetSimulator()->Simulate(
Simulator::SimulationType::BitstreamFrontDoor, sim_tool,
Expand Down Expand Up @@ -1292,7 +1296,8 @@ bool Compiler::RegisterCommands(TclInterpreter* interp, bool batchMode) {
sim_tool = sim;
sim_tool_valid = true;
} else if (arg == "rtl" || arg == "gate" || arg == "pnr" ||
arg == "bitstream_fd" || arg == "bitstream_bd") {
arg == "timed_pnr" || arg == "bitstream_fd" ||
arg == "bitstream_bd") {
sim_type = arg;
} else if (arg == "clean") {
clean = true;
Expand Down Expand Up @@ -1329,7 +1334,9 @@ bool Compiler::RegisterCommands(TclInterpreter* interp, bool batchMode) {
"simulate_rtl_th", Action::SimulateGate, compiler);
status = wthread->start();
if (!status) return TCL_ERROR;
} else if (sim_type == "pnr") {
} else if (sim_type == "pnr" || sim_type == "timed_pnr") {
compiler->GetSimulator()->SetTimedSimulation(
(sim_type == "timed_pnr"));
WorkerThread* wthread = new WorkerThread(
"simulate_rtl_th", Action::SimulatePNR, compiler);
status = wthread->start();
Expand Down
59 changes: 55 additions & 4 deletions src/Simulation/Simulator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -256,7 +256,16 @@ bool Simulator::RegisterCommands(TclInterpreter* interp) {
auto auto_testbench = [](void* clientData, Tcl_Interp* interp, int argc,
const char* argv[]) -> int {
Simulator* simulator = (Simulator*)clientData;
int result = simulator->GenerateAutoTestbench();
float clock_period = 5.0;
for (int i = 1; i < argc; i++) {
std::string arg = argv[i];
if (arg == "-clock_period") {
i++;
arg = argv[i];
clock_period = std::atof(arg.c_str());
}
}
int result = simulator->GenerateAutoTestbench(clock_period);
if (result != 0) {
return TCL_ERROR;
}
Expand All @@ -267,7 +276,7 @@ bool Simulator::RegisterCommands(TclInterpreter* interp) {
return ok;
}

int Simulator::GenerateAutoTestbench() {
int Simulator::GenerateAutoTestbench(float clock_period) {
Message("##################################################");
Message("Generating automatic RTL vs gate-level testbench ");
Message("##################################################");
Expand All @@ -281,7 +290,8 @@ int Simulator::GenerateAutoTestbench() {
std::string command = std::string(python3Path.string()) + " " +
std::string(scriptPath.string()) + " " +
ProjManager()->projectName() + " " +
std::string(path.string());
std::string(path.string()) + " " + std::to_string(100) +
" " + std::to_string(clock_period);
FileUtils::WriteToFile(CommandLogFile("comp"), command);
int status = m_compiler->ExecuteAndMonitorSystemCommand(
command, "auto-testbench.log", false, workingDir);
Expand Down Expand Up @@ -652,6 +662,34 @@ std::string Simulator::TopModuleCmd(SimulatorType type) {
return "Invalid";
}

std::string Simulator::SimulationTypeMacro(SimulationType sim_type,
SimulatorType simulator_type) {
switch (simulator_type) {
case SimulatorType::Verilator:
case SimulatorType::Icarus:
case SimulatorType::Questa:
case SimulatorType::VCS:
case SimulatorType::Xcelium: {
std::string result = MacroDirective(simulator_type);
switch (sim_type) {
case SimulationType::RTL:
return (result + "RTL_SIM=1");
case SimulationType::Gate:
return (result + "GATE_SIM=1");
case SimulationType::PNR:
return (result + "PNR_SIM=1");
case SimulationType::BitstreamFrontDoor:
return (result + "BITSTREAM_FD_SIM=1");
case SimulationType::BitstreamBackDoor:
return (result + "BITSTREAM_BD_SIM=1");
}
}
case SimulatorType::GHDL:
return "";
}
return "Invalid";
}

std::string Simulator::LanguageDirective(SimulatorType type,
Design::Language lang) {
switch (type) {
Expand Down Expand Up @@ -1072,7 +1110,7 @@ bool Simulator::SimulateRTL(SimulatorType type) {
}
fileList += lang_file.second + " ";
}

fileList = SimulationTypeMacro(SimulationType::RTL, type) + " " + fileList;
fileList = SimulationFileList(SimulationType::RTL, type, fileList);
fileList = StringUtils::rtrim(fileList);

Expand Down Expand Up @@ -1102,6 +1140,7 @@ bool Simulator::SimulateGate(SimulatorType type) {
Message("##################################################");

std::string fileList = SimulationFileList(SimulationType::Gate, type);
fileList = SimulationTypeMacro(SimulationType::Gate, type) + " " + fileList;

std::string netlistFile;
switch (m_compiler->GetNetlistType()) {
Expand Down Expand Up @@ -1197,6 +1236,16 @@ bool Simulator::SimulatePNR(SimulatorType type) {
for (auto path : m_gateSimulationModels) {
fileList += LibraryFileDirective(type) + path.string() + " ";
}

fileList = SimulationTypeMacro(SimulationType::PNR, type) + " " + fileList;

if (IsTimedSimulation()) {
fileList = " -DTIMED_SIM=1 " + fileList;
if (type == SimulatorType::Icarus) {
fileList = " -gspecify " + fileList;
}
}

fileList = StringUtils::rtrim(fileList);

bool status = SimulationJob(SimulationType::PNR, type, fileList);
Expand Down Expand Up @@ -1227,6 +1276,8 @@ bool Simulator::SimulateBitstream(SimulationType sim_type, SimulatorType type) {
LanguageDirective(type, Design::Language::SYSTEMVERILOG_2012);
auto designTopModule = m_compiler->DesignTopModule();

fileList = SimulationTypeMacro(sim_type, type) + " " + fileList;

if (sim_type == SimulationType::BitstreamBackDoor) {
if (!ProjManager()->SimulationFiles().empty() &&
type == SimulatorType::Icarus) {
Expand Down
9 changes: 7 additions & 2 deletions src/Simulation/Simulator.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -115,15 +115,19 @@ class Simulator {
void UserSimulationType(SimulationType simulation, SimulatorType simulator);
SimulatorType UserSimulationType(SimulationType simulation, bool& ok) const;

int GenerateAutoTestbench();
int GenerateAutoTestbench(float clock_period);

bool IsTimedSimulation() { return m_timed_simulation; }
void SetTimedSimulation(bool timed) { m_timed_simulation = timed; }

protected:
virtual bool SimulateRTL(SimulatorType type);
virtual bool SimulateGate(SimulatorType type);
virtual bool SimulatePNR(SimulatorType type);
virtual bool SimulateBitstream(SimulationType sim_type,
SimulatorType simulator_type);

virtual std::string SimulationTypeMacro(SimulationType sim_type,
SimulatorType simulator_type);
virtual std::string SimulatorName(SimulatorType type);
virtual std::filesystem::path SimulatorExecPath(SimulatorType type);
virtual std::string IncludeDirective(SimulatorType type);
Expand Down Expand Up @@ -171,6 +175,7 @@ class Simulator {
std::map<SimulationType, std::string> m_waveFiles;
std::map<SimulationType, SimulatorType> m_simulatorTypes;
SimulationType m_simType = SimulationType::RTL;
bool m_timed_simulation = false;
};

} // namespace FOEDAG
Expand Down

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