Fix bug in resource checking (#1686)

* Fix bug in resource checking

* More detail in root bank clkmux resource

* Incremented patch version

---------

Co-authored-by: chungshien-chai <chungshien-chai@users.noreply.github.com>

CMakeLists.txt

@@ -39,7 +39,7 @@ set(VERSION_MINOR 0)
 # Add the spdlog directory to the include path
 include_directories(${CMAKE_CURRENT_SOURCE_DIR}/third_party/spdlog/include ${CMAKE_CURRENT_SOURCE_DIR}/third_party/exprtk ${CMAKE_CURRENT_SOURCE_DIR}/third_party/scope_guard) 
 
-set(VERSION_PATCH 421)
+set(VERSION_PATCH 422)
 
 
 option(

src/Configuration/ModelConfig/ModelConfig_IO.cpp

@@ -1101,8 +1101,15 @@ void ModelConfig_IO::allocate_and_set_root_bank_routing() {
  POST_DEBUG_MSG(2, "%s %s", module.c_str(), name.c_str());
  std::string src_location = get_location(name);
  PIN_INFO src_pin_info = get_pin_info(src_location);
- std::pair<bool, std::string> status =
- m_resource->use_root_bank_clkmux(name, src_location, src_pin_info);
+ std::string sub_resource = "CORE";
+ if (module == "I_SERDES" && instance["parameters"].contains("DPA_MODE")) {
+ if (instance["parameters"]["DPA_MODE"] == "DPA" ||
+ instance["parameters"]["DPA_MODE"] == "CDR") {
+ sub_resource = "CDR";
+ }
+ }
+ std::pair<bool, std::string> status = m_resource->use_root_bank_clkmux(
+ name, src_location, sub_resource, src_pin_info);
  if (status.first) {
  POST_DEBUG_MSG(3, "Resource: %s", status.second.c_str());
  // Set ROOT_BANK_CLKMUX
@@ -1914,7 +1921,7 @@ PIN_INFO ModelConfig_IO::get_pin_info(const std::string& name) {
  std::vector<CFG_Python_OBJ> results =
  m_python->run_file("config", "get_pin_info",
  std::vector<CFG_Python_OBJ>({CFG_Python_OBJ(name)}));
- CFG_ASSERT_MSG(results.size() == 10,
+ CFG_ASSERT_MSG(results.size() == 11,
  "Expect Python get_pin_info() function return 10 arguments, "
  "but found %ld",
  results.size());
@@ -1926,13 +1933,14 @@ PIN_INFO ModelConfig_IO::get_pin_info(const std::string& name) {
  CFG_ASSERT(results[5].type == CFG_Python_OBJ::TYPE::INT);
  CFG_ASSERT(results[6].type == CFG_Python_OBJ::TYPE::STR);
  CFG_ASSERT(results[7].type == CFG_Python_OBJ::TYPE::STR);
- CFG_ASSERT(results[8].type == CFG_Python_OBJ::TYPE::INT);
+ CFG_ASSERT(results[8].type == CFG_Python_OBJ::TYPE::STR);
  CFG_ASSERT(results[9].type == CFG_Python_OBJ::TYPE::INT);
- return PIN_INFO(results[0].get_str(), results[1].get_u32(),
- results[2].get_bool(), results[3].get_u32(),
- results[4].get_u32(), results[5].get_u32(),
- results[6].get_str(), results[7].get_str(),
- results[8].get_u32(), results[9].get_u32());
+ CFG_ASSERT(results[10].type == CFG_Python_OBJ::TYPE::INT);
+ return PIN_INFO(
+ results[0].get_str(), results[1].get_u32(), results[2].get_bool(),
+ results[3].get_u32(), results[4].get_u32(), results[5].get_u32(),
+ results[6].get_str(), results[7].get_str(), results[8].get_str(),
+ results[9].get_u32(), results[10].get_u32());
 }
 
 /*

src/Configuration/ModelConfig/ModelConfig_IO_resource.cpp

@@ -189,19 +189,19 @@ bool ModelConfig_IO_RESOURCE::use_resource(const std::string& resource,
 */
 std::pair<bool, std::string> ModelConfig_IO_RESOURCE::use_root_bank_clkmux(
  const std::string& module, const std::string& location,
- PIN_INFO& pin_info) {
+ const std::string& sub_resource, PIN_INFO& pin_info) {
+ CFG_ASSERT(sub_resource == "CORE" || sub_resource == "CDR");
+ std::string resource = CFG_print(
+ "%s(%s)", pin_info.root_bank_mux_resource.c_str(), sub_resource.c_str());
  std::pair<bool, std::string> status;
- if (m_root_bank_clkmuxes.find(pin_info.root_bank_mux_location) !=
- m_root_bank_clkmuxes.end()) {
+ if (m_root_bank_clkmuxes.find(resource) != m_root_bank_clkmuxes.end()) {
  status = std::make_pair(
- false,
- CFG_print(
- "%s is already used by %s", pin_info.root_bank_mux_location.c_str(),
- m_root_bank_clkmuxes.at(pin_info.root_bank_mux_location).c_str()));
+ false, CFG_print("%s is already used by %s", resource.c_str(),
+ m_root_bank_clkmuxes.at(resource).c_str()));
  } else {
- m_root_bank_clkmuxes[pin_info.root_bank_mux_location] =
+ m_root_bank_clkmuxes[resource] =
  CFG_print("module %s (location: %s)", module.c_str(), location.c_str());
- status = std::make_pair(true, pin_info.root_bank_mux_location);
+ status = std::make_pair(true, resource);
  }
  return status;
 }

src/Configuration/ModelConfig/ModelConfig_IO_resource.h

@@ -29,7 +29,8 @@ namespace FOEDAG {
 struct PIN_INFO {
  PIN_INFO(const std::string& in0, uint32_t in1, bool in2, uint32_t in3,
  uint32_t in4, uint32_t in5, const std::string& in6,
- const std::string& in7, uint32_t in8, uint32_t in9)
+ const std::string& in7, const std::string& in8, uint32_t in9,
+ uint32_t in10)
  : type(in0),
  bank(in1),
  is_clock(in2),
@@ -38,8 +39,9 @@ struct PIN_INFO {
  ab_io(in5),
  ab_name(in6),
  root_bank_mux_location(in7),
- root_bank_mux_core_input_index(in8),
- root_mux_input_index(in9) {
+ root_bank_mux_resource(in8),
+ root_bank_mux_core_input_index(in9),
+ root_mux_input_index(in10) {
  CFG_ASSERT((type == "BOOT_CLOCK" && ab_name.size() == 0) ||
  ab_name.size() == 1);
  }
@@ -51,6 +53,7 @@ struct PIN_INFO {
  const uint32_t ab_io = 0;
  const std::string ab_name = "";
  const std::string root_bank_mux_location = "";
+ const std::string root_bank_mux_resource = "";
  const uint32_t root_bank_mux_core_input_index = 0;
  const uint32_t root_mux_input_index = 0;
 };
@@ -93,9 +96,9 @@ struct ModelConfig_IO_RESOURCE {
  const std::string& type);
  bool use_resource(const std::string& resource,
  const std::string& instantiator, const std::string& name);
- std::pair<bool, std::string> use_root_bank_clkmux(const std::string& module,
-   const std::string& location,
-   PIN_INFO& pin_info);
+ std::pair<bool, std::string> use_root_bank_clkmux(
+ const std::string& module, const std::string& location,
+ const std::string& sub_resource, PIN_INFO& pin_info);
  // Fail-safe mechanism
  void backup();
  void restore();

tests/unittest/ModelConfig/apis/config_attributes.mapping.json

@@ -380,6 +380,7 @@
  " ab_io = 0",
  " ab_name = ''",
  " root_bank_mux_location = ''",
+ " root_bank_mux_resource = ''",
  " root_bank_mux_core_input_index = 0",
  " root_mux_input_index = 0",
  " if name.find('BOOT_CLOCK#') == 0:",
@@ -398,10 +399,11 @@
  " ab_name = '%c' % (ord('A') + ab_io)",
  " root_name = 'u_GBOX_HP_40X2' if type == 'HP' else ('u_GBOX_HV_40X2_VL' if type == 'HVL' else 'u_GBOX_HV_40X2_VR')",
  " root_bank_mux_location = '%s.u_gbox_root_bank_clkmux_%d' % (root_name, bank)",
+ " root_bank_mux_resource = '%s (Bank %s)' % (root_bank_mux_location, ab_name)",
  " root_bank_mux_core_input_index = index - (20 * ab_io)",
  " root_mux_input_index = 0 if type == 'HP' else (8 if type == 'HVL' else 16)",
  " root_mux_input_index += ((2 * bank) + ab_io)",
- " return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_core_input_index, root_mux_input_index]",
+ " return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_resource, root_bank_mux_core_input_index, root_mux_input_index]",
  "def fclk_use_pll_resource(fclk) :",
  " pll_resource = 0", 
  " if fclk.find('hvl_fclk_') == 0 :",
@@ -556,7 +558,6 @@
  "__check_dpa_mode_parameter__",
  "__check_clock_phase_parameter__",
  "__check_pll_parameter__",
- "__check_pll_clock_pin_resource__",
  "__update_fabric_clock_resource__"
  ],
  "__check_fabric_clock_resource__" : {

tests/unittest/ModelConfig/golden/config.py

@@ -7,6 +7,7 @@ def get_pin_info(name) :
  ab_io = 0
  ab_name = ''
  root_bank_mux_location = ''
+ root_bank_mux_resource = ''
  root_bank_mux_core_input_index = 0
  root_mux_input_index = 0
  if name.find('BOOT_CLOCK#') == 0:
@@ -25,10 +26,11 @@ def get_pin_info(name) :
  ab_name = '%c' % (ord('A') + ab_io)
  root_name = 'u_GBOX_HP_40X2' if type == 'HP' else ('u_GBOX_HV_40X2_VL' if type == 'HVL' else 'u_GBOX_HV_40X2_VR')
  root_bank_mux_location = '%s.u_gbox_root_bank_clkmux_%d' % (root_name, bank)
+ root_bank_mux_resource = '%s (Bank %s)' % (root_bank_mux_location, ab_name)
  root_bank_mux_core_input_index = index - (20 * ab_io)
  root_mux_input_index = 0 if type == 'HP' else (8 if type == 'HVL' else 16)
  root_mux_input_index += ((2 * bank) + ab_io)
- return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_core_input_index, root_mux_input_index]
+ return [type, bank, is_clock, index, pair_index, ab_io, ab_name, root_bank_mux_location, root_bank_mux_resource, root_bank_mux_core_input_index, root_mux_input_index]
 def fclk_use_pll_resource(fclk) :
  pll_resource = 0
  if fclk.find('hvl_fclk_') == 0 :

tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json

@@ -52,12 +52,14 @@
  " Warning: Not able to route clock-capable pin clk_buf40 (location:HR_2_CC_38_19P) to gearbox module o_serdes_clk clock (module:O_SERDES_CLK) (location:HR_2_8_4P). Reason: Attemp to use FCLK: hvl_fclk_1_A, but it had been used by PLL:HR_1_CC_38_19P",
  "Allocate ROOT BANK routing resource (and set configuration attributes)",
  " CLK_BUF clk_buf00",
- " Resource: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0",
+ " Resource: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 (Bank A)(CORE)",
  " CLK_BUF $clkbuf$top.$ibuf_clk20",
- " Warning: Fail to route the clock. Reason: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 is already used by module clk_buf00 (location: HP_1_CC_18_9P)",
+ " Resource: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 (Bank B)(CORE)",
  "Set CLKBUF remaining configuration attributes (FCLK)",
  " Set FCLK configuration attributes",
  " CLKBUF clk_buf00 (location:HP_1_CC_18_9P) use hp_fclk_0_B",
+ " Set FCLK configuration attributes",
+ " Skip for HP_1_CC_38_19P",
  "Allocate PLL resource (and set PLLREF configuration attributes)",
  " PLL pll00 (location:HP_1_CC_18_9P) uses FCLK 'hvl_fclk_0_B'",
  " Pin resource: 3, PLL FCLK requested resource: 1, PLL availability: 3",
@@ -126,6 +128,16 @@
  " Property",
  " Rule I_BUF.IOSTANDARD",
  " Mismatch",
+ " Module: CLK_BUF ($clkbuf$top.$ibuf_clk20)",
+ " Object: clk20",
+ " Parameter",
+ " Property",
+ " Rule CLK_BUF.GBOX_TOP",
+ " Match",
+ " Rule CLK_BUF.ROOT_BANK_CLKMUX",
+ " Match",
+ " Rule CLK_BUF.ROOT_MUX",
+ " Match",
  " Module: I_BUF ($ibuf$top.$ibuf_din00)",
  " Object: din00",
  " Parameter",
@@ -625,7 +637,7 @@
  "__pll_enable__" : "1",
  "__pll_resource__" : "0",
  "__validation__" : "TRUE",
- "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__check_pll_clock_pin_resource__,__update_fabric_clock_resource__"
+ "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__"
  },
  {
  "module" : "I_BUF",
@@ -767,6 +779,17 @@
  "ROUTE_TO_FABRIC_CLK" : "6"
  },
  "config_attributes" : [
+ {
+ "CLK_BUF" : "GBOX_TOP_SRC==DEFAULT"
+ },
+ {
+ "CLK_BUF" : "ROOT_BANK_SRC==B --#MUX=18",
+ "__location__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0"
+ },
+ {
+ "ROOT_MUX_SEL" : "1",
+ "__location__" : "u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6"
+ }
  ]
  }
  },
@@ -786,8 +809,12 @@
  },
  "errors" : [
  ],
- "__validation__" : "FALSE",
- "__validation_msg__" : "Fail to route the clock. Reason: u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 is already used by module clk_buf00 (location: HP_1_CC_18_9P)"
+ "__AB__" : "B",
+ "__ROOT_BANK_MUX_LOCATION__" : "u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0",
+ "__ROOT_BANK_MUX__" : "18",
+ "__ROOT_MUX__" : "1",
+ "__validation__" : "TRUE",
+ "__validation_msg__" : "Pass:__clock_pin_is_valid__,__check_fabric_clock_resource__,__update_fabric_clock_resource__"
  },
  {
  "module" : "I_BUF",

tests/unittest/ModelConfig/golden/model_config.ppdb.json

@@ -58,11 +58,11 @@
  " CLKBUF $clkbuf$top.$ibuf_clk2 (location:HR_5_CC_38_19P)",
  "Allocate ROOT BANK routing resource (and set configuration attributes)",
  " CLK_BUF $clkbuf$top.$ibuf_clk0",
- " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0",
+ " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_0 (Bank B)(CORE)",
  " CLK_BUF $clkbuf$top.$ibuf_clk2",
- " Resource: u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1",
+ " Resource: u_GBOX_HV_40X2_VR.u_gbox_root_bank_clkmux_1 (Bank B)(CORE)",
  " I_SERDES i_serdes",
- " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1",
+ " Resource: u_GBOX_HV_40X2_VL.u_gbox_root_bank_clkmux_1 (Bank A)(CDR)",
  "Set CLKBUF remaining configuration attributes (FCLK)",
  " Set FCLK configuration attributes",
  " CLKBUF $clkbuf$top.$ibuf_clk0 (location:HR_1_CC_38_19P) use hvl_fclk_0_A",
@@ -699,7 +699,7 @@
  "__pll_enable__" : "0",
  "__pll_resource__" : "0",
  "__validation__" : "TRUE",
- "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__check_pll_clock_pin_resource__,__update_fabric_clock_resource__"
+ "__validation_msg__" : "Pass:__pll_clock_pin_is_valid__,__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__"
  },
  {
  "module" : "I_BUF",
@@ -1755,7 +1755,7 @@
  "__pll_enable__" : "0",
  "__pll_resource__" : "1",
  "__validation__" : "TRUE",
- "__validation_msg__" : "Pass:__check_fabric_clock_resource__,__check_pll_parameter__,__check_pll_clock_pin_resource__,__update_fabric_clock_resource__"
+ "__validation_msg__" : "Pass:__check_fabric_clock_resource__,__check_pll_parameter__,__update_fabric_clock_resource__"
  },
  {
  "module" : "I_BUF_DS",

tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit

@@ -2944,17 +2944,17 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_19 [HP_1_CC_38_19P]
  PEER_IS_ON - Addr: 0x00001415, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  TX_CLOCK_IO - Addr: 0x00001416, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  TX_DDR_MODE - Addr: 0x00001417, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
- TX_BYPASS - Addr: 0x00001419, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
+ TX_BYPASS - Addr: 0x00001419, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] }
  TX_CLK_PHASE - Addr: 0x0000141A, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  TX_DLY - Addr: 0x0000141C, Size: 6, Value: (0x00000000) 0
  RX_DDR_MODE - Addr: 0x00001422, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
- RX_BYPASS - Addr: 0x00001424, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
+ RX_BYPASS - Addr: 0x00001424, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] }
  RX_DLY - Addr: 0x00001425, Size: 6, Value: (0x00000000) 0
  RX_DPA_MODE - Addr: 0x0000142B, Size: 2, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  RX_MIPI_MODE - Addr: 0x0000142D, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  TX_MODE - Addr: 0x0000142E, Size: 1, Value: (0x00000000) 0
  RX_MODE - Addr: 0x0000142F, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
- RX_CLOCK_IO - Addr: 0x00001430, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
+ RX_CLOCK_IO - Addr: 0x00001430, Size: 1, Value: (0x00000001) 1 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT], $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:GBOX_TOP_SRC==DEFAULT] }
  DFEN - Addr: 0x00001431, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  SR - Addr: 0x00001432, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] }
  PE - Addr: 0x00001433, Size: 1, Value: (0x00000000) 0 { $ibuf$top.$ibuf_clk20 [I_BUF] [I_BUF:WEAK_KEEPER==NONE] }
@@ -3899,7 +3899,7 @@ Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_0 []
  Attributes:
  CDR_CLK_ROOT_SEL_B - Addr: 0x00001A88, Size: 5, Value: (0x00000000) 0
  CDR_CLK_ROOT_SEL_A - Addr: 0x00001A8D, Size: 5, Value: (0x00000000) 0
- CORE_CLK_ROOT_SEL_B - Addr: 0x00001A92, Size: 5, Value: (0x00000000) 0
+ CORE_CLK_ROOT_SEL_B - Addr: 0x00001A92, Size: 5, Value: (0x00000012) 18 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==B --#MUX=18] [from HP_1_CC_38_19P] }
  CORE_CLK_ROOT_SEL_A - Addr: 0x00001A97, Size: 5, Value: (0x00000012) 18 { clk_buf00 [CLK_BUF] [CLK_BUF:ROOT_BANK_SRC==A --#MUX=18] [from HP_1_CC_18_9P] }
 Block u_GBOX_HP_40X2.u_gbox_root_bank_clkmux_1 []
  Attributes:
@@ -3927,7 +3927,7 @@ Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_5 []
  ROOT_MUX_SEL - Addr: 0x00001ACE, Size: 6, Value: (0x0000003F) 63
 Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_6 []
  Attributes:
- ROOT_MUX_SEL - Addr: 0x00001AD4, Size: 6, Value: (0x0000003F) 63
+ ROOT_MUX_SEL - Addr: 0x00001AD4, Size: 6, Value: (0x00000001) 1 { $clkbuf$top.$ibuf_clk20 [CLK_BUF] [ROOT_MUX_SEL:1] [from HP_1_CC_38_19P] }
 Block u_GBOX_HP_40X2.u_gbox_clkmux_52x1_left_7 []
  Attributes:
  ROOT_MUX_SEL - Addr: 0x00001ADA, Size: 6, Value: (0x0000003F) 63