Latest Release_Sim_1.5.7 & Fix EDA-3293

[AYYAZmayo]

Motivate of the pull request

• To address an existing issue. If so, please add GH or Jira ID here: <>
  EDA-3293/EDA-3258
• Breaking new feature. If so, please describe details in the description part.

Which submodule does this change impact ?

• Backend
• FOEDAG_rs
• IP_Catalog
• Raptor_Tools
• yosys_verific_rs
• zephyr-rapidsi-dev
• Github CI

What does this pull request change?

• This brings the latest FPGA_PRIMITVIES_MODELS Release_sim_1.5.7
• It fixes the issue of EDA-3293, (automatically handling the illegal I_BUF/O_BUF instantiation)

Verified that the following tests passed locally before PR was created.

• make tests/batch_all
• RunGJC.tcl

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.