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Merge pull request #115 from os-fpga/blocking_to_nonblocking_ram_tran…
RIC Workflow #457: Commit a111fbb pushed by alaindargelas
September 25, 2024 22:25 2m 12s main
September 25, 2024 22:25 2m 12s
Merge pull request #115 from os-fpga/blocking_to_nonblocking_ram_tran…
Surelog Synlig GHDL Workflow #457: Commit a111fbb pushed by alaindargelas
September 25, 2024 22:25 20m 41s main
September 25, 2024 22:25 20m 41s
Merge pull request #115 from os-fpga/blocking_to_nonblocking_ram_tran…
Read Verilog Workflow #457: Commit a111fbb pushed by alaindargelas
September 25, 2024 22:25 2s main
September 25, 2024 22:25 2s
Blocking to non-blocking RAM inference transform
Surelog Synlig GHDL Workflow #456: Pull request #115 opened by alaindargelas
September 25, 2024 22:25 20m 2s blocking_to_nonblocking_ram_transform
September 25, 2024 22:25 20m 2s
Blocking to non-blocking RAM inference transform
Surelog Synlig GHDL Workflow #455: Commit 4c8adc2 pushed by alaindargelas
September 25, 2024 22:19 19m 58s blocking_to_nonblocking_ram_transform
September 25, 2024 22:19 19m 58s
Merge pull request #114 from os-fpga/error_unknown_param
Surelog Synlig GHDL Workflow #454: Commit b572bd3 pushed by alaindargelas
September 24, 2024 22:06 19m 59s main
September 24, 2024 22:06 19m 59s
Merge pull request #114 from os-fpga/error_unknown_param
RIC Workflow #454: Commit b572bd3 pushed by alaindargelas
September 24, 2024 22:06 2m 8s main
September 24, 2024 22:06 2m 8s
Merge pull request #114 from os-fpga/error_unknown_param
Read Verilog Workflow #454: Commit b572bd3 pushed by alaindargelas
September 24, 2024 22:06 3s main
September 24, 2024 22:06 3s
Error out on unknown parameter override
Surelog Synlig GHDL Workflow #453: Pull request #114 opened by alaindargelas
September 24, 2024 22:05 20m 10s error_unknown_param
September 24, 2024 22:05 20m 10s
Error out on unknown parameter override
RIC Workflow #453: Pull request #114 opened by alaindargelas
September 24, 2024 22:05 2m 14s error_unknown_param
September 24, 2024 22:05 2m 14s
Error out on unknown parameter override
Read Verilog Workflow #453: Pull request #114 opened by alaindargelas
September 24, 2024 22:05 2s error_unknown_param
September 24, 2024 22:05 2s
Error out on unknown parameter override
RIC Workflow #452: Commit 37a7d40 pushed by alaindargelas
September 24, 2024 22:05 2m 9s error_unknown_param
September 24, 2024 22:05 2m 9s
Error out on unknown parameter override
Surelog Synlig GHDL Workflow #452: Commit 37a7d40 pushed by alaindargelas
September 24, 2024 22:05 19m 50s error_unknown_param
September 24, 2024 22:05 19m 50s
Error out on unknown parameter override
Read Verilog Workflow #452: Commit 37a7d40 pushed by alaindargelas
September 24, 2024 22:05 2s error_unknown_param
September 24, 2024 22:05 2s
Merge pull request #113 from os-fpga/bits_in_gen_block
RIC Workflow #451: Commit 6b4046b pushed by alaindargelas
September 24, 2024 16:01 2m 11s main
September 24, 2024 16:01 2m 11s
Merge pull request #113 from os-fpga/bits_in_gen_block
Read Verilog Workflow #451: Commit 6b4046b pushed by alaindargelas
September 24, 2024 16:01 2s main
September 24, 2024 16:01 2s
Merge pull request #113 from os-fpga/bits_in_gen_block
Surelog Synlig GHDL Workflow #451: Commit 6b4046b pushed by alaindargelas
September 24, 2024 16:01 19m 57s main
September 24, 2024 16:01 19m 57s
Fix bits and size in gen blocks
RIC Workflow #450: Pull request #113 opened by alaindargelas
September 24, 2024 16:01 2m 14s bits_in_gen_block
September 24, 2024 16:01 2m 14s
Fix bits and size in gen blocks
Read Verilog Workflow #450: Pull request #113 opened by alaindargelas
September 24, 2024 16:01 2s bits_in_gen_block
September 24, 2024 16:01 2s