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452 changes: 255 additions & 197 deletions Cargo.lock

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ clap = "4.2"
const_format = "0.2"
crossbeam-channel = "0.5"
ctrlc = "3.2"
dropshot = "0.16.2"
dropshot = "0.16.4"
erased-serde = "0.4"
errno = "0.2.8"
escargot = "0.5.8"
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2 changes: 1 addition & 1 deletion bin/propolis-server/src/lib/migrate/memx.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ use crate::migrate::codec;

// Validates the parameters from a fetch, offer, or xfer.
pub(crate) fn validate_bitmap(start: u64, end: u64, bits: &[u8]) -> bool {
if start % 4096 != 0 || end % 4096 != 0 {
if !start.is_multiple_of(4096) || !end.is_multiple_of(4096) {
return false;
}
if end <= start {
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2 changes: 1 addition & 1 deletion lib/propolis/src/hw/nvme/cmds.rs
Original file line number Diff line number Diff line change
Expand Up @@ -942,7 +942,7 @@ impl Iterator for PrpIter<'_> {
match self.get_next() {
Ok(res) => Some(res),
Err(e) => {
probes::nvme_prp_error!(|| (e));
probes::nvme_prp_error!(|| e);
self.error = Some(e);
None
}
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4 changes: 2 additions & 2 deletions lib/propolis/src/hw/nvme/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -766,7 +766,7 @@ impl PciNvme {
CtrlrReg::DoorBellAdminSQ => {
// 32-bit register but ignore reserved top 16-bits
let val = wo.read_u32() as u16;
probes::nvme_doorbell_admin_sq!(|| (val));
probes::nvme_doorbell_admin_sq!(|| val);
let state = self.state.lock().unwrap();

if !state.ctrl.cc.enabled() {
Expand All @@ -788,7 +788,7 @@ impl PciNvme {
CtrlrReg::DoorBellAdminCQ => {
// 32-bit register but ignore reserved top 16-bits
let val = wo.read_u32() as u16;
probes::nvme_doorbell_admin_cq!(|| (val));
probes::nvme_doorbell_admin_cq!(|| val);
let state = self.state.lock().unwrap();

if !state.ctrl.cc.enabled() {
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2 changes: 1 addition & 1 deletion lib/propolis/src/hw/virtio/block.rs
Original file line number Diff line number Diff line change
Expand Up @@ -166,7 +166,7 @@ impl PciVirtioBlock {
}
}
VIRTIO_BLK_T_FLUSH => {
probes::vioblk_flush_enqueue!(|| (rid));
probes::vioblk_flush_enqueue!(|| rid);
Ok(self.block_tracking.track(
block::Request::new_flush(),
CompletionPayload { rid, chain },
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2 changes: 1 addition & 1 deletion lib/propolis/src/vcpu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -374,7 +374,7 @@ impl Vcpu {
// that can be done.
}
}
probes::vm_entry!(|| (self.id as u32));
probes::vm_entry!(|| self.id as u32);
let _res = unsafe { self.hdl.ioctl(bhyve_api::VM_RUN, &mut entry)? };
probes::vm_exit!(|| (self.id as u32, exit.rip, exit.exitcode as u32));

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2 changes: 1 addition & 1 deletion phd-tests/framework/src/disk/crucible.rs
Original file line number Diff line number Diff line change
Expand Up @@ -219,7 +219,7 @@ impl Inner {
const GIBIBYTE: u64 = 1 << 30;

assert!(EXTENT_SIZE > block_size.bytes());
assert!(EXTENT_SIZE % block_size.bytes() == 0);
assert!(EXTENT_SIZE.is_multiple_of(block_size.bytes()));

let disk_size_gib = match read_only_parent {
// If there's a read-only parent, ensure the disk is large enough to
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2 changes: 1 addition & 1 deletion rust-toolchain.toml
Original file line number Diff line number Diff line change
Expand Up @@ -2,5 +2,5 @@
# We choose a specific toolchain (rather than "stable") for repeatability. The
# intent is to keep this up-to-date with recently-released stable Rust.

channel = "1.88.0"
channel = "1.90.0"
profile = "default"
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