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v0.21.0

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@sylvlecl sylvlecl released this 15 Jun 08:41

Release notes

Features

  • Use PowSyBl Core 4.9.0 (#540, #557)
    • Replace p0 and q0 of batteries by targetP and targetQ (#547)
    • Distributed active power calculation (#544)
  • Update version numbers in readme.md (#521)
  • Rename user object to property (#524)
  • Remove property (#528)
  • Outer loops persistent context (#530)
  • Make predefined results for AC and DC sensitivity analyses coherent (#523)
  • Use OpenLoadFlow parameter addRatioToLinesWithDifferentNominalVoltageAtBothEnds everywhere (#531)
  • Remove transformer voltage controls when no PV buses at non controlled side (#482)
  • Injection sensitivity from bus or busbar section ID (#536)
  • Contingency refactoring: support of all types of contingencies for AC sensitivity and security analysis (#493)
  • Fix LfVscConverterStationImpl design (#546)
  • Current limit violations detection in DC security analysis (#549)
  • Same provider name for LF, SA and Sensi (#556)

Refactorings and coverage

  • Clean phase control outer loop code (#527)
  • Equation system index optimization (#435)
  • Add AC equations unit tests (a540e79)
  • Add unit test for sensi value non regression (#548)
  • Improve testing of AC voltage sensitivities (#539)
  • Assert active power, reactive power and current consistency (#545)
  • AC equations refactoring (#543)
  • Optimize cos and sin of ksi (#551)
  • Improve transformer voltage control unit testing (#427)
  • DC Sensitivity analysis: add unit test on IEEE14 (#555)

Bug fixes

  • Fix outer loops cleanup (#514)
  • Fixed cases where Q could exceed the generators limits (#529)
  • Fix "No such edge in graph" exception (#534)
  • Fix AC sensitivity analysis in case of a branch contingency breaking connectivity (#541)
  • GraphDecrementalConnectivity fixes:
    • Cache lazily the main connected component in Even-Shiloach implementation (#537)
    • Handle loops in Even-Shiloach implementation (#538)
    • Cut the branch only if connected (8c8064e)