AXI4+ATOP on chip memory slave #115
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The conflict in the |
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Rebased onto current master. |
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Timeout for the complete CI seems no longer to be sufficient enough long when adding |
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Rebased onto current master for ci fix by #129. Ci will time-out as testing for |
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added 20 commits
January 19, 2021 11:17
added 8 commits
January 19, 2021 11:36
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This was referenced Aug 5, 2022
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This adds two modules:
axi_to_mem: Salve module, max throughout simultaneous read/writes 50%, read or write 100%.axi_to_mem_banked: With enough banks 100% throughput with simultaneous reads/writes.Notes to Bender:
For the dependencies
pulp-platform/tech_cells_generichas been directly added. In there thetc_srammodule is used for the testbench to serve a memory model.-> For all conflicts in the dependency tree of Bender, the versions specified by the Bender.yml of this repo has to be used.
Edit: Now bender.lock is also checked in so CI should pass now
This depends on changes form #116.