AXI4 on chip memory slave

[micprog]

Rebase of the relevant changes in #115 on the current master

This adds two modules:

• axi_to_mem: Slave module, max throughout simultaneous read/writes 50%, read or write 100%.
• axi_to_mem_banked: With enough banks 100% throughput with simultaneous reads/writes.

Notes to Bender:
For the dependencies pulp-platform/tech_cells_generic has been directly added. In there the tc_sram module is used for the testbench to serve a memory model.

Open tasks

• Rework mem_to_banks to ensure no writes are issued with strb='0. While not illegal, this can cause issues (e.g. when converting back to APB3) and unnecessary contention on an interconnect
• Add an interleaved variant to allow reads and writes to bypass each other
• Add a split variant to completely separate the read and write channel to individual mem ports when connecting to an interconnect

[andreaskurth]

Thanks for the effort of updating this code and getting it into a PR, @micprog! I highly appreciate it.

However, I cannot allocate a block of time to review more than 2k LoC. Please split this into multiple PRs. For instance, the first PR should simply add the latest version of axi_to_mem.

[micprog]

Merged with #244 and #248 and #256

[thommythomaso]

Archived: https://github.com/pulp-platform/axi/releases/tag/archive%2F2022-08-05_axi_to_mem_rebase