updated fpga build to Vitis / Vivado v2023.2

[peteasa]

In this commit I have not changed the original .bin file that remains unchanged. I have also left the associated reports in out folder unchanged.

This commit will allow people to use Vitis / Vivado v2023.2 to build the pyrpl fpga. By bringing the build system to v2023 it allows more recent Vitis tools to be used more easily.

Also it pulls in more recent board definitions for more recent RedPitaya boards.

Also it builds the overlay device tree blob that is needed to load fpga and matching device tree onto the RedPitaya boards.

I have tested the generated .bin file and the generated .dtbo device tree with the latest nose tests and have not seen any significant problems.

I have run the IIR filter code with a butterworth low pass filter and get the same results are with the original pyrpl .bin file and the current eco system v2 pyrpl .bin file.

[michaelcroquette]

Ok I'm trying to test your PRs now. The issue with this one is that it doesn't work for Vivado 2024.2 which is the most recent one. Is there a specific reason to choose the 2023.2 version ?

[peteasa]

Vivado 2024.2 will work with Vitis flow that replaces the xsct commands... I have not yet installed 2024 so I can't test this yet.. But I have a python Vitis script ready but without the overlay device tree creation part. I will push that script up if you want to add the overlay device tree creation bit and update the Makefile.

Basically the pl.dtsi overlay device tree has the plugin part added. This will be missing if the Vitis flow is used without the "DT Overlay" selected
/dts-v1/; /plugin/; &fpga_full { firmware-name = "fpga.bit.bin"; };
To achieve this with Vitis GUI, follow the Embedded Component and import the hardware https://docs.amd.com/r/en-US/ug1400-vitis-embedded/Creating-a-Platform-Component-from-XSA but remember to select Generate Device Tree Blob (DTB) and also select "DT Overlay"

You then get a python script that you can use with the script interface rather than the xsct commands in the Makefile

vitis -s vitis_create_fsbl.py
after running the device tree appears in
vitis_proj/redpitaya/export/redpitaya/hw/sdt
Of course the Makefile also has to be updated with the version change so that the correct device-tree-xlnx-xilinx-v$(VITIS_VER) is cloned and the DTS_DIR = vitis_proj/redpitaya/export/redpitaya/hw/sdt has to be updated

[peteasa]

Thinking about it .. I would expect that the latest Vitis would still support the xsct commands..

it doesn't work for Vivado 2024.2

did you try the simplest change.. just update the version in the Makefile
VITIS_VER = 2024.2

and in fpga/ip/system_bd.tcl
set scripts_vivado_version 2024.2

[michaelcroquette]

You're right it works ! I didn't modified the fpga/ip/system_bd.tcl file so that was blocking. I will perform the pytest just to make sure and merge the PR. Thanks for all your work !

[peteasa]

I am in the process of downloading / installing v2024.2 so I will be able to help if there are any problems!

[peteasa]

I have created the v2024.2 fpga and used it so it seems ok. I also looked at the ecosystem devicetree and did a comparison with the v2024.2 generated devicetree. Whilst a few things have been moved about the only significant difference is that the eco system pyrpl devicetree has the extra two S_AXI_HP2 and S_AXI_HP3 interfaces enabled (in the devicetree these are afi2 and afi3).