pyrpl-fpga · peteasa · Feb 9, 2025 · Feb 14, 2025 · Feb 14, 2025 · Feb 19, 2025
diff --git a/pyrpl/fpga/Makefile b/pyrpl/fpga/Makefile
@@ -3,30 +3,74 @@
 # Authors: Matej Oblak, Iztok Jeras
 # (C) Red Pitaya 2013-2015
 #
-# Red Pitaya FPGA/SoC Makefile 
+# Red Pitaya FPGA/SoC Makefile
 #
 
+VIVADO_VER := $(shell vivado -version | head -n 1 | sed -e 's/ (/_/g' | sed -e 's/ /_/g' | sed -e 's/)//g')
+
+PARENT  = ../../..
+VITIS_VER = 2024.2
+DTG     = $(PARENT)/device-tree-xlnx-xilinx-v$(VITIS_VER)
+
+# Red Pitaya FPGA repo
+RP_VER  = Release-2024.3
+RPFPGA  = $(PARENT)/RedPitaya-FPGA
+
 # build results
-FPGA_BIN=out/red_pitaya.bin
+OUT_DIR=out
+FPGA_BIN=$(OUT_DIR)/red_pitaya.bin
+FPGA_DTBO=$(OUT_DIR)/red_pitaya.dtbo
 
 #logfile for stdout and stderr
 LOG=>> fpga.log 2>&1
 
 # Vivado from Xilinx provides IP handling, FPGA compilation
-# hsi (hardware software interface) provides software integration
+# Vitis / xsct provide software integration
 # both tools are run in batch mode with an option to avoid log/journal files
 VIVADO = vivado -nolog -nojournal -mode batch
+DTS_DIR = sdk/dts
+PL_DEVICE_TREE = $(DTS_DIR)/pl.dtsi
 
-all: clean $(FPGA_BIN) postclean
+all: $(FPGA_BIN) $(FPGA_DTBO) postclean
 
-clean:
-	rm -rf out .Xil .srcs sdk
+ifeq ($(VIVADO_VER),)
+$(error "Vivado not detected: setup environment with source /opt/Xilinx/Vivado/$(VITIS_VER)/settings64.sh")
+endif
+
+ifneq ($(VIVADO_VER),vivado_v$(VITIS_VER)_64-bit)
+$(error "Vivado version $(VIVADO_VER) consider changing DTG version $(VITIS_VER)")
+endif
 
 $(FPGA_BIN):
 	$(VIVADO) -source red_pitaya_vivado.tcl $(LOG)
 
+# required for the device tree creation
+$(DTG):
+	git clone https://github.com/Xilinx/device-tree-xlnx.git $(DTG)
+	@cd $(DTG); git checkout xilinx_v$(VITIS_VER) $(LOG)
+
+# required for the device tree creation
+$(RPFPGA):
+	git clone https://github.com/RedPitaya/RedPitaya-FPGA.git $(RPFPGA)
+	@cd $(RPFPGA); git checkout $(RP_VER) $(LOG)
+
+# device tree overlay creation
+$(FPGA_DTBO): $(DTG) $(RPFPGA)
+	xsct xsct_hsi_dtb.tcl DTG_VER=$(VITIS_VER) $(LOG)
+
+#fix bug with #address-cells and #size-cells for overlay
+	sed -i 's/#address-cells/\/\/#address-cells/g' $(DTS_DIR)/pl.dtsi
+	sed -i 's/#size-cells/\/\/#size-cells/g' $(DTS_DIR)/pl.dtsi
+	sed -i 's/red_pitaya.bit.bin/fpga.bit.bin/g' $(DTS_DIR)/pl.dtsi
+
+	dtc -@ -O dtb -o $(FPGA_DTBO) -i $(DTS_DIR) -i $(RPFPGA)/dts $(PL_DEVICE_TREE) $(LOG)
+	dtc -I dtb -O dts $(OUT_DIR)/red_pitaya.dtbo -o $(OUT_DIR)/red_pitaya.dts $(LOG)
+
 postclean:
-	mv *.xml out/
-	mv *.prm out/
-	mv *.html out/
-	mv *.log out/
+	cp $(FPGA_BIN) $(FPGA_DTBO) .
+	cp .gen/sources_1/bd/system/ip/system_processing_system7_0/*.html $(OUT_DIR)
+	cp sdk/red_pitaya.hwh $(OUT_DIR)
+	mv *.log $(OUT_DIR)
+
+clean:
+	rm -rf out .Xil .srcs .gen sdk
diff --git a/pyrpl/fpga/README.md b/pyrpl/fpga/README.md
@@ -1,57 +1,67 @@
 # Directory structure
 
-|  path           | contents
-|-----------------|-------------------------------------------------------------
-| `fpga/Makefile` | main Makefile, used to run FPGA related tools
-| `fpga/*.tcl`    | TCL scripts to be run inside FPGA tools
-| `fpga/archive/` | archive of XZ compressed FPGA bit files
-| `fpga/doc/`     | documentation (block diagrams, address space, ...)
-| `fpga/ip/`      | third party IP, for now Zynq block diagrams
-| `fpga/rtl/`     | Verilog (SystemVerilog) "Register-Transfer Level"
-| `fpga/sdc/`     | "Synopsys Design Constraints" contains Xilinx design constraints
-| `fpga/sim/`     | simulation scripts
-| `fpga/tbn/`     | Verilog (SystemVerilog) "test bench"
-|                 |
-| `fpga/hsi/`     | "Hardware Software Interface" contains FSBL (First Stage Boot Loader) and DTS (Design Tree) builds
+|  path             | contents
+|-------------------|-------------------------------------------------------------
+| `fpga/Makefile`   | main Makefile, used to run FPGA related tools
+| `fpga/*.tcl`      | TCL scripts to be run inside FPGA tools
+| `fpga/ip/`        | third party IP, for now Zynq block diagrams
+| `fpga/rtl/`       | Verilog (SystemVerilog) "Register-Transfer Level"
+| `fpga/sdc/`       | "Synopsys Design Constraints" contains Xilinx design constraints
+| `fpga/sim/`       | simulation scripts
+| `fpga/tbn/`       | Verilog (SystemVerilog) "test bench"
+|                   |
+| `fpga/sdk/`       | generated red_pitaya.xsa file used to create a Vitis project
+| `fpga/out`        | generated logs and other significant artifacts from the build
 
 # Build process
 
-Xilinx Vivado 2015.4 (including SDK) is required. If installed at the default location, then the next command will properly configure system variables:
+> [!NOTE]
+> First consider using the fpga build scripts in [RedPitaya/Makefile.x86](https://github.com/RedPitaya/RedPitaya/blob/master/Makefile.x86) that supports all the different RedPitaya board types using the [RedPitaya-FPGA](https://github.com/RedPitaya/RedPitaya-FPGA) hdl code rather than this fpga build.
+
+Assuming you have a specific requirement to use this hdl code rather than the RedPitaya-FPGA hdl code in your design make sure that you update the part number and constraints sdc file specific to your target board in `fpga/red_pitaya_vivado.tcl`
+```
+set part xc7z010clg400-1
+read_xdc                          $path_sdc/red_pitaya.xdc
+```
+
+Xilinx Vitis / Vivado 2023.2 is required. If installed at the default location, then the next command will properly configure system variables:
 ```bash
-. /opt/Xilinx/Vivado/2015.4/settings64.sh
+. /opt/Xilinx/Vivado/2023.2/settings64.sh
+```
+
+If you need to update to a more recent version of Vitis / Vivado then update the Vivado version in `fpga/ip/system_bd.tcl` - be prepared to fix up various build tcl scripts to replace depreciated tcl commands
+```
+set scripts_vivado_version 2023.2
 ```
 
 The default mode for building the FPGA is to run a TCL script inside Vivado. Non project mode is used, to avoid the generation of project files, which are too many and difficult to handle. This allows us to only place source files and scripts under version control.
 
-The next scripts perform various tasks:
+The next scripts perform various tasks for the xc7z010clg400-1 part:
 
 | TCL script                      | action
 |---------------------------------|---------------------------------------------
-| `red_pitaya_hsi_dram_test.tcl`  | should create the `zynq_dram_test` but the produced binary can not be run from a SD card
-| `red_pitaya_hsi_dts.tcl`        | creates device tree sources
-| `red_pitaya_hsi_fsbl.tcl`       | creates FSBL executable binary
 | `red_pitaya_vivado_project.tcl` | creates a Vivado project for graphical editing
 | `red_pitaya_vivado.tcl`         | creates the bitstream and reports
 
-To generate a bit file, reports, device tree and FSBL, run these two commands:
+To generate a redpitaya.bin file for the xc7z010clg400-1 part, redpitaya.dtbo device tree, reports, run these two commands:
 ```bash
-source /opt/Xilinx/Vivado/2015.4/settings64.sh
+source /opt/Xilinx/Vivado/2023.2/settings64.sh
 make
 ```
 
 # Device tree
+> [!NOTE]
+> You do not need to build the .bin file or the device tree to use Pyrpl.  They are provided pre-built.
 
-Device tree is used by Linux to describe features and address space of memory mapped hardware attached to the CPU.
-
-Running `make` inside this directory will create a device tree source and some include files:
-
-| device tree file | contents
-|------------------|------------------------------------------------------------
-| `zynq-7000.dtsi` | description of peripherals inside PS (processing system)
-| `pl.dtsi`        | description of AXI attached peripherals inside PL (programmable logic)
-| `system.dts`     | description of all peripherals, includes the above `*.dtsi` files
-
-To enable some Linux drivers (Ethernet, XADC, I2C EEPROM, SPI, GPIO and LED) the device tree source is patched using `../patches/devicetree.patch`.
+Device tree is used by Linux to describe features and address space of memory mapped hardware attached to the CPU.  It can (optionally) be installed onto the RedPitaya board with the redpitaya.bin file generated (specify the full path to the files).  In this example assuming the generated .bin and .dtbo files are in the same directory as the python code:
+```
+from pyrpl import Pyrpl
+p = Pyrpl(hostname=HOSTNAME,
+    reloadfpga = True, filename = 'red_pitaya.bin',
+    dtbo_filename = 'red_pitaya.dtbo'
+    )
+```
+The pre-built .bin file and device tree are used if these files are not specified.  You can avoid reloading the fpga files each time you run your script by setting reloadfpga = False.  If you use the config, configuration file attribute, then the attributes that are used are stored in a .yaml file in the PYRPL_USER_DIR so next time you start your application the settings including reloadfpga will be restored.
 
 # Signal mapping
 

diff --git a/pyrpl/fpga/clockInfo.txt b/pyrpl/fpga/clockInfo.txt
@@ -0,0 +1,10 @@
+-------------------------------------
+| Tool Version : Vivado v.2024.2
+| Date         : Wed Feb 19 13:25:22 2025
+| Host         : fontana
+| Design       : design_1
+| Device       : xc7z010-clg400-1--
+-------------------------------------
+
+For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
+
diff --git a/pyrpl/fpga/ip/system.bd b/pyrpl/fpga/ip/system.bd
@@ -1595,7 +1595,7 @@
       </spirit:componentInstance>
       <spirit:componentInstance>
         <spirit:instanceName>xadc</spirit:instanceName>
-        <spirit:componentRef spirit:library="ip" spirit:name="xadc_wiz" spirit:vendor="xilinx.com" spirit:version="3.2"/>
+        <spirit:componentRef spirit:library="ip" spirit:name="xadc_wiz" spirit:vendor="xilinx.com" spirit:version="3.3"/>
         <spirit:configurableElementValues>
           <spirit:configurableElementValue spirit:referenceId="bd:xciName">system_xadc_0</spirit:configurableElementValue>
           <spirit:configurableElementValue spirit:referenceId="XADC_STARUP_SELECTION">independent_adc</spirit:configurableElementValue>

diff --git a/pyrpl/fpga/ip/system_bd.tcl b/pyrpl/fpga/ip/system_bd.tcl
@@ -10,7 +10,7 @@
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2015.4
+set scripts_vivado_version 2024.2
 set current_vivado_version [version -short]
 
 if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
@@ -343,18 +343,20 @@ CONFIG.PCW_USE_S_AXI_HP1 {1} \
  ] $processing_system7
 
   # Create instance: xadc, and set properties
-  set xadc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.2 xadc ]
+  set xadc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc ]
   set_property -dict [ list \
-CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \
-CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} \
-CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} \
-CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} \
-CONFIG.CHANNEL_ENABLE_VP_VN {true} \
-CONFIG.ENABLE_AXI4STREAM {false} \
-CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
-CONFIG.SEQUENCER_MODE {Off} \
-CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
-CONFIG.XADC_STARUP_SELECTION {independent_adc} \
+   CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \
+   CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} \
+   CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} \
+   CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} \
+   CONFIG.CHANNEL_ENABLE_VP_VN {true} \
+   CONFIG.ENABLE_AXI4STREAM {false} \
+   CONFIG.ENABLE_RESET {false} \
+   CONFIG.EXTERNAL_MUX_CHANNEL {VP_VN} \
+   CONFIG.INTERFACE_SELECTION {Enable_AXI} \
+   CONFIG.SEQUENCER_MODE {Off} \
+   CONFIG.SINGLE_CHANNEL_SELECTION {TEMPERATURE} \
+   CONFIG.XADC_STARUP_SELECTION {independent_adc} \
  ] $xadc
 
   # Create instance: xlconstant, and set properties

diff --git a/pyrpl/fpga/make.bat b/pyrpl/fpga/make.bat
@@ -3,6 +3,6 @@
 @RD /S /Q .srcs
 @RD /S /Q sdk
 
-c:/Xilinx/Vivado/2015.4/bin/vivado.bat -nolog -nojournal -mode tcl -source red_pitaya_vivado.tcl
+c:/Xilinx/Vivado/2024.2/bin/vivado.bat -nolog -nojournal -mode tcl -source red_pitaya_vivado.tcl
 
 echo compilation finished