Skip to content

Conversation

@arlesniak
Copy link
Contributor

Enable optim_bf16_stochastic_round_correctness test for XPU

@pytorch-bot
Copy link

pytorch-bot bot commented Sep 24, 2025

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/3055

Note: Links to docs will display an error until the docs builds have been completed.

❗ 1 Active SEVs

There are 1 currently active SEVs. If your PR is affected, please view them below:

✅ No Failures

As of commit b1121ac with merge base f92b898 (image):
💚 Looks good so far! There are no failures yet. 💚

This comment was automatically generated by Dr. CI and updates every 15 minutes.

@meta-cla meta-cla bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Sep 24, 2025
torch.testing.assert_close(p2, p1)

@parametrize("device", _DEVICES)
def test_optim_bf16_stochastic_round_correctness(self):
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

device arg is not added to the function

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@arlesniak _DEVICES is the global variable in this file, I don't think your change is needed.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The "test_optim_bf16_stochastic_round_correctness" should be parametrized with _DEVICES global variable, which contains other devices (XPU if detected). Without the PR changes the choice was cuda, cpu only.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Are you sure? According to this code,https://github.com/pytorch/ao/blob/main/torchao/utils.py#L143 when the xpu is available in your ENV, the _DEVICES will contain the XPU.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Let me be more precise. You're right, the _DEVICES list will contain XPU if detected. Without the PR changes the test will be triggered once with the hardcoded device choice - cuda or cpu: https://github.com/pytorch/ao/blob/main/test/test_low_bit_optim.py#L423, regardless of _DEVICES content.
After the PR changes, the test will be triggered separately for every device from the _DEVICES including XPU (similiar to some other parametrized tests i.e. test_quantize_8bit_with_qmap_correctness etc).

@liangan1 liangan1 self-requested a review September 29, 2025 07:08
@arlesniak arlesniak force-pushed the arlesniak/enable_optim_sr_test_xpu branch from cfd22f6 to b1121ac Compare October 22, 2025 13:26
@liangan1 liangan1 added topic: improvement Use this tag if this PR is an improvement (doesn't fit into any of the other categories) ciflow/xpu label used to trigger xpu CI jobs labels Nov 4, 2025
@pytorch-bot
Copy link

pytorch-bot bot commented Nov 4, 2025

To add the ciflow label ciflow/xpu please first approve the workflows that are awaiting approval (scroll to the bottom of this page).

This helps ensure we don't trigger CI on this PR until it is actually authorized to do so. Please ping one of the reviewers if you do not have access to approve and run workflows.

@pytorch-bot pytorch-bot bot removed the ciflow/xpu label used to trigger xpu CI jobs label Nov 4, 2025
@liangan1 liangan1 requested a review from jerryzh168 December 1, 2025 01:07
@liangan1 liangan1 merged commit 69ce0fd into pytorch:main Dec 5, 2025
20 of 21 checks passed
vkuzo added a commit that referenced this pull request Dec 10, 2025
* add MXFP8 all gather support

* added TODO for future feature

* remove emoji from comment

* fixed ruff formating

* fixed ruff formatting

* add mxfp8 and nvfp4 to Llama eval scripts (#3394)

Update

[ghstack-poisoned]

* flip mx inference scaling setting to RCEIL (#3428)

* Update

[ghstack-poisoned]

* Update

[ghstack-poisoned]

* Update

[ghstack-poisoned]

* add CLAUDE.local.md to gitignore (#3437)

Summary:

taking claude code for a more thorough spin, will start with local
instructions and will see what makes sense to upstream

Test Plan:

Reviewers:

Subscribers:

Tasks:

Tags:

* bump python version in tutorial ci workflow (#3439)

* [CPU] Reland qconv fp8 fusion passes (#3433)

* [Reland][PT2E][X86] Add Inductor fusion passes of float8 qconv for X86Inductor backend

* add torch version check for Qconv FP8 UTs

* fix format issue

* Skip tests for ROCm

---------

Co-authored-by: Sun, Jiayi <jiayi.sun@intel.com>

* Int8Tensor migration cleanup (#3407)

* Int8Tensor migration

Summary:

This PR creates a new Int8Tensor and updates the configs to use the new
Int8Tensor flow

Test Plan:

To ensure BC:
```
pytest test/quantization/test_quant_api.py
```

To test new Int8Tensor:
```
pytest test/quantization/quantize_/workflows/int8/test_int8_tensor.py
```

Reviewers:

Subscribers:

Tasks:

Tags:

* ruff fixes

* add init

* fix ruff again

* update

* wip

* undo update tests

* fix ruff

* fix varname

* fix typing

* add tests

* fix dtype

* fix ci

* address granularity cr

* update _choose_quant_func_and_quantize_tensor

* make block size required attribute

* made dtype required as well

* address nits

* skip per tensor weight only test for now

* [xpu][test] Port 2 test/dtypes_{floatx, bitpacking} UT files to intel XPU (#3368)

* enable test/dtypes/test_bitpacking.py on intel xpu

* enable test/dtypes/test_floatx.py

* enable test/dtypes/test_floatx.py

* fix format issue

* fix format issue

* update _DEVICES

* [xpu][test] Port 2 test/quantization/pt2e/test_{quantize_pt2e, quantize_pt2e_qat} UT files to intel XPU (#3405)

* add test/quantization/pt2e/test_quantize_pt2e.py

* add test/quantization/pt2e/test_quantize_pt2e.py

* test/quantization/pt2e/test_quantize_pt2e_qat.py

* test/quantization/pt2e/test_quantize_pt2e_qat.py

* fix format issue

* update format

* increase timeout for xpu

* [Intel GPU] Enable optim SR test (#3055)

* updated test with rebase changes

* added checks to run only on CUDA with compatibility >=9

* updated test for H100

* added test to workflow

---------

Co-authored-by: Vasiliy Kuznetsov <vkuzo@users.noreply.github.com>
Co-authored-by: Daniel Vega-Myhre <danvm@meta.com>
Co-authored-by: Xia Weiwen <weiwen.xia@intel.com>
Co-authored-by: Sun, Jiayi <jiayi.sun@intel.com>
Co-authored-by: Jesse Cai <jessecai@meta.com>
Co-authored-by: xiangdong <40376367+zxd1997066@users.noreply.github.com>
Co-authored-by: Artur Lesniak <artur.lesniak@intel.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. topic: improvement Use this tag if this PR is an improvement (doesn't fit into any of the other categories)

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants