[xpu][test] Port 2 test/dtypes_{floatx, bitpacking} UT files to intel XPU #3368
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/3368
Note: Links to docs will display an error until the docs builds have been completed. ✅ No FailuresAs of commit b6a2c80 with merge base 257d18a ( This comment was automatically generated by Dr. CI and updates every 15 minutes. |
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test/dtypes/test_floatx.py
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| _DEVICES = ( | ||
| ["cpu"] | ||
| + (["cuda"] if torch.cuda.is_available() else []) | ||
| + (["xpu"] if torch.xpu.is_available() else []) | ||
| ) |
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why not do torch.accelerator.is_available here (and change cuda to get_current_accelerator_device)?
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updated to use torch.accelerator.is_available
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* add MXFP8 all gather support * added TODO for future feature * remove emoji from comment * fixed ruff formating * fixed ruff formatting * add mxfp8 and nvfp4 to Llama eval scripts (#3394) Update [ghstack-poisoned] * flip mx inference scaling setting to RCEIL (#3428) * Update [ghstack-poisoned] * Update [ghstack-poisoned] * Update [ghstack-poisoned] * add CLAUDE.local.md to gitignore (#3437) Summary: taking claude code for a more thorough spin, will start with local instructions and will see what makes sense to upstream Test Plan: Reviewers: Subscribers: Tasks: Tags: * bump python version in tutorial ci workflow (#3439) * [CPU] Reland qconv fp8 fusion passes (#3433) * [Reland][PT2E][X86] Add Inductor fusion passes of float8 qconv for X86Inductor backend * add torch version check for Qconv FP8 UTs * fix format issue * Skip tests for ROCm --------- Co-authored-by: Sun, Jiayi <jiayi.sun@intel.com> * Int8Tensor migration cleanup (#3407) * Int8Tensor migration Summary: This PR creates a new Int8Tensor and updates the configs to use the new Int8Tensor flow Test Plan: To ensure BC: ``` pytest test/quantization/test_quant_api.py ``` To test new Int8Tensor: ``` pytest test/quantization/quantize_/workflows/int8/test_int8_tensor.py ``` Reviewers: Subscribers: Tasks: Tags: * ruff fixes * add init * fix ruff again * update * wip * undo update tests * fix ruff * fix varname * fix typing * add tests * fix dtype * fix ci * address granularity cr * update _choose_quant_func_and_quantize_tensor * make block size required attribute * made dtype required as well * address nits * skip per tensor weight only test for now * [xpu][test] Port 2 test/dtypes_{floatx, bitpacking} UT files to intel XPU (#3368) * enable test/dtypes/test_bitpacking.py on intel xpu * enable test/dtypes/test_floatx.py * enable test/dtypes/test_floatx.py * fix format issue * fix format issue * update _DEVICES * [xpu][test] Port 2 test/quantization/pt2e/test_{quantize_pt2e, quantize_pt2e_qat} UT files to intel XPU (#3405) * add test/quantization/pt2e/test_quantize_pt2e.py * add test/quantization/pt2e/test_quantize_pt2e.py * test/quantization/pt2e/test_quantize_pt2e_qat.py * test/quantization/pt2e/test_quantize_pt2e_qat.py * fix format issue * update format * increase timeout for xpu * [Intel GPU] Enable optim SR test (#3055) * updated test with rebase changes * added checks to run only on CUDA with compatibility >=9 * updated test for H100 * added test to workflow --------- Co-authored-by: Vasiliy Kuznetsov <vkuzo@users.noreply.github.com> Co-authored-by: Daniel Vega-Myhre <danvm@meta.com> Co-authored-by: Xia Weiwen <weiwen.xia@intel.com> Co-authored-by: Sun, Jiayi <jiayi.sun@intel.com> Co-authored-by: Jesse Cai <jessecai@meta.com> Co-authored-by: xiangdong <40376367+zxd1997066@users.noreply.github.com> Co-authored-by: Artur Lesniak <artur.lesniak@intel.com>
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For #2917, This PR is targeted to port test/dtypes/test_floatx.py and test/dtypes/test_bitpacking.py to intel XPU.